Details | Last modification | View Log | RSS feed
| Rev | Author | Line No. | Line |
|---|---|---|---|
| 1 | - | 1 | OrCAD LOGIC COMPILER v2.01 N 12/09/94 (Source file .\PLD\#0167.PLD) |
| 2 | |||
| 3 | 1 || FILE: #0167.PLD |
||
| 4 | 2 || PROJ: 20170501 |
||
| 5 | 3 || FD-02 FDC/ATA/DMA BOARD |
||
| 6 | 4 || |
||
| 7 | 5 || PART: G18V10-#0167 |
||
| 8 | 6 || |
||
| 9 | 7 || DEV : GAL18V10 |
||
| 10 | 8 || |
||
| 11 | 9 || DESC: DMA CONTROL |
||
| 12 | 10 || |
||
| 13 | 11 | |
||
| 14 | 12 |GAL18V10 |
||
| 15 | 13 | |
||
| 16 | 14 || INPUT |
||
| 17 | 15 | 1:CLK, 2:AEN0, 3:HRQ0, 4:RES, 5:DMA, 6:FDC, 7:HRQ1, 8:AEN1, 9:EOP1, |
||
| 18 | 16 || OUTPUT |
||
| 19 | 17 | 19:Q0, 18:HLD0, 17:OE0, 16:PRES, 15:TC, 14:MGE, 13:OE1, 12:HLD1, 11:Q1 |
||
| 20 | 18 | |
||
| 21 | 19 | ACTIVE-LOW: OE0, OE1 |
||
| 22 | 20 | |
||
| 23 | 21 | SIGNATURE: "0167 " |
||
| 24 | 22 | |
||
| 25 | 23 || -------------------------------------------------------- |
||
| 26 | 24 || |
||
| 27 | 25 | Q[1..0] = CLK // Q[1..0] + 1 || Q0 = CLK/2, Q1 = CLK/4 |
||
| 28 | 26 | AEN0X = AEN0 & DMA' & FDC || dma0 enable |
||
| 29 | 27 | AEN1X = AEN1 & DMA' & FDC' || dma1 enable |
||
| 30 | 28 | OE0 = AEN0X || dma0 bus enable |
||
| 31 | 29 | OE1 = AEN1X || dma1 bus enable |
||
| 32 | 30 | HLD0 = HRQ0 & DMA' & FDC || dma0 hold bus |
||
| 33 | 31 | HLD1 = HRQ1 & DMA' & FDC' || dma1 hold bus |
||
| 34 | 32 | TC = EOP1' || terminal count for fdc |
||
| 35 | 33 | PRES = RES' || reset positive pulse |
||
| 36 | 34 | MGE = AEN0X # AEN1X || ram gate enable for cpu access |
||
| 37 | |||
| 38 | |||
| 39 | |||
| 40 | I201 No warnings. |
||
| 41 | |||
| 42 | |||
| 43 | |||
| 44 | I203 Memory usage 77K |
||
| 45 | I204 Elapsed time 1 second |
||
| 46 | OrCAD DEVICE FITTER v2.01 12/09/94 (Source file .\PLD\#0167.PLA) |
||
| 47 | |||
| 48 | |||
| 49 | |||
| 50 | |||
| 51 | |||
| 52 | |||
| 53 | |||
| 54 | |||
| 55 | 79 Q0 Q1' |
||
| 56 | |||
| 57 | Q0 2 Q0' |
||
| 58 | |||
| 59 | |||
| 60 | |||
| 61 | |||
| 62 | 50 DMA' FDC' AEN1 |
||
| 63 | |||
| 64 | OE1 60 DMA' FDC' AEN1 |
||
| 65 | |||
| 66 | |||
| 67 | |||
| 68 | |||
| 69 | |||
| 70 | |||
| 71 | |||
| 72 | |||
| 73 | |||
| 74 | |||
| 75 | |||
| 76 | |||
| 77 | |||
| 78 | |||
| 79 | |||
| 80 | |||
| 81 | 1. CLK 0 - - - High (Clock) |
||
| 82 | 2. AEN0 4 - - - High |
||
| 83 | 3. HRQ0 8 - - - High |
||
| 84 | |||
| 85 | 5. DMA 16 - - - High |
||
| 86 | 6. FDC 20 - - - High |
||
| 87 | 7. HRQ1 24 - - - High |
||
| 88 | 8. AEN1 28 - - - High |
||
| 89 | 9. EOP1 34 86 9 0 High (Registered) |
||
| 90 | 11. Q1 33 77 9 2 High (Registered) |
||
| 91 | 12. HLD1 30 68 9 1 High (Three-state) |
||
| 92 | 13. OE1 27 59 9 1 Low (Three-state) |
||
| 93 | 14. MGE 22 48 11 2 High (Three-state) |
||
| 94 | 15. TC 18 37 11 1 High (Three-state) |
||
| 95 | 16. PRES 14 28 9 1 High (Three-state) |
||
| 96 | 17. OE0 11 19 9 1 Low (Three-state) |
||
| 97 | 18. HLD0 6 10 9 1 High (Three-state) |
||
| 98 | 19. Q0 3 1 9 1 High (Registered) |
||
| 99 | 21. - - 0 1 0 |
||
| 100 | 22. - - 95 1 0 |
||
| 101 | ---- ---- |
||
| 102 | 96 11 (11%) |
||
| 103 | |||
| 104 | |||
| 105 | I200 No fatal errors found in source code (device phase). |
||
| 106 | I201 No warnings. |
||
| 107 | |||
| 108 | |||
| 109 | OrCAD DEVICE |
||
| 110 | Type: GAL18V10 |
||
| 111 | |||
| 112 | |||
| 113 | |||
| 114 | L0036 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 * |
||
| 115 | L0072 11 01 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 * |
||
| 116 | L0360 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 * |
||
| 117 | L0396 11 11 11 11 01 11 11 11 10 11 01 11 11 11 11 11 11 11 * |
||
| 118 | L0684 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 * |
||
| 119 | L0720 11 11 01 11 11 11 11 11 10 11 01 11 11 11 11 11 11 11 * |
||
| 120 | L1008 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 * |
||
| 121 | L1044 11 11 11 11 11 11 10 11 11 11 11 11 11 11 11 11 11 11 * |
||
| 122 | L1332 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 * |
||
| 123 | L1368 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 10 * |
||
| 124 | L1728 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 * |
||
| 125 | L1764 11 11 01 11 11 11 11 11 10 11 01 11 11 11 11 11 11 11 * |
||
| 126 | L1800 11 11 11 11 11 11 11 11 10 11 10 11 11 11 01 11 11 11 * |
||
| 127 | L2124 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 * |
||
| 128 | L2160 11 11 11 11 11 11 11 11 10 11 10 11 11 11 01 11 11 11 * |
||
| 129 | L2448 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 * |
||
| 130 | L2484 11 11 11 11 11 11 11 11 10 11 10 11 01 11 11 11 11 11 * |
||
| 131 | L2772 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 * |
||
| 132 | L2808 11 01 11 11 11 11 11 11 11 11 11 11 11 11 11 11 10 11 * |
||
| 133 | L2844 11 10 11 11 11 11 11 11 11 11 11 11 11 11 11 11 01 11 * |
||
| 134 | L3456 10 11 01 11 11 11 01 11 10 11 00 11 00 00 00 11 00 01 * |
||
| 135 | L3492 00 11 01 10 00 11 01 11 00 10 00 00 00 10 00 00 00 10 * |
||
| 136 | L3528 00 00 00 10 00 00 * |
||
| 137 | C5DFC* |
||
| 138 | |||
| 139 | I202 4/25/17 9:11 pm (Tuesday) |
||
| 140 | I203 Memory usage 5K |
||
| 141 | I204 Elapsed time 1 second |
||
| 142 |