Details | Last modification | View Log | RSS feed
| Rev | Author | Line No. | Line |
|---|---|---|---|
| 1 | - | 1 | || FILE: #0166.PLD |
| 2 | || PROJ: 20170501 |
||
| 3 | || FD-02 FDC/ATA/DMA BOARD |
||
| 4 | || |
||
| 5 | || PART: G26CV12-#0166 |
||
| 6 | || |
||
| 7 | || DEV : GAL26CV12 |
||
| 8 | || |
||
| 9 | || DESC: RAM ACCESS CONTROL |
||
| 10 | || |
||
| 11 | | |
||
| 12 | |GAL26CV12 |
||
| 13 | | |
||
| 14 | || INPUT |
||
| 15 | | 1:CA0, 2:MA0, 3:CX2, 4:PHI2, 5:MW0, 6:DMA, 8:PHI0, 9:OE0, 10:OE1, |
||
| 16 | | 11:S1M, 12:ATA0, 13:FDC, 14:ALT, 28:RW, |
||
| 17 | || OUTPUT |
||
| 18 | | 15:MWE, 16:MRD, 17:CEL, 18:CEH, 19:CE1, 20:OEL, 22:OEH, 23:BE0, |
||
| 19 | | 24:BE1, 25:EV, 26:ODD, 27:AEN |
||
| 20 | | |
||
| 21 | | ACTIVE-LOW: MWE, MRD, CEL, CEH, CE1, OEL, OEH, BE0, BE1, EV, ODD |
||
| 22 | | |
||
| 23 | | |
||
| 24 | | SIGNATURE: "0166 " |
||
| 25 | | |
||
| 26 | || -------------------------------------------------------- |
||
| 27 | || common signals when dma disabled (DMA = 1 => cpu access) |
||
| 28 | || |
||
| 29 | | MMR0 = CX2' & DMA & OE0 & RW & PHI2 || cpu read ram |
||
| 30 | | MMR1 = CX2' & DMA & OE1 & RW & PHI2 || cpu read ram |
||
| 31 | | MMW0 = CX2' & DMA & OE0 & RW' & PHI2 & MW0 || cpu read ram (02) |
||
| 32 | | MMW1 = CX2' & DMA & OE0 & RW' & PHI0 & MW0' || cpu read ram (00) |
||
| 33 | | MMW2 = CX2' & DMA & OE1 & RW' & PHI2 & MW0 || cpu read ram (02) |
||
| 34 | | MMW3 = CX2' & DMA & OE1 & RW' & PHI0 & MW0' || cpu read ram (00) |
||
| 35 | | MMRD = MMR0 # MMR1 || cpu read ram strobe |
||
| 36 | | MMWR = MMW0 # MMW1 # MMW2 # MMW3 || cpu write ram strobe |
||
| 37 | || |
||
| 38 | | MLC0 = CX2' & DMA & OE0 & S1M' & CA0' || cpu access 1Mb even ram |
||
| 39 | | MLC1 = CX2' & DMA & OE1 & S1M' & CA0' || cpu access 1Mb even ram |
||
| 40 | | MHC0 = CX2' & DMA & OE0 & S1M' & CA0 || cpu access 1Mb odd ram |
||
| 41 | | MHC1 = CX2' & DMA & OE1 & S1M' & CA0 || cpu access 1Mb odd ram |
||
| 42 | | MLCC = MLC0 # MLC1 || cpu access 1Mb even ram |
||
| 43 | | MHCC = MHC0 # MHC1 || cpu access 1Mb odd ram |
||
| 44 | | MLCCP = (MLC0 # MLC1) & PHI2 || cpu access 1Mb even ram |
||
| 45 | | MHCCP = (MHC0 # MHC1) & PHI2 || cpu access 1Mb odd ram |
||
| 46 | | M2C0 = CX2' & DMA & OE0 & S1M & PHI2 || cpu access 128Kb ram |
||
| 47 | | M2C1 = CX2' & DMA & OE1 & S1M & PHI2 || cpu access 128Kb ram |
||
| 48 | | M2CC = (M2C0 # M2C1) || cpu access 128Kb ram |
||
| 49 | || |
||
| 50 | || common signals when dma enabled (DMA = 0) |
||
| 51 | | M1D0 = DMA' & OE0' & FDC || dma0 access 1Mb ram |
||
| 52 | | M1D1 = DMA' & OE1' & FDC' & ALT' || dma1 access 1Mb ram |
||
| 53 | | M2D1 = DMA' & OE1' & FDC' & ALT || dma1 access 128kb ram |
||
| 54 | || |
||
| 55 | || output signals |
||
| 56 | | MWE = DMA ?? MMWR || write ram strobe 3-states |
||
| 57 | | MRD = DMA ?? MMRD || read ram strobe 3-states |
||
| 58 | | CEL = MLCCP # M1D0 # M1D1 || enable even ram 1Mb |
||
| 59 | | CEH = MHCCP # M1D0 # M1D1 || enable odd ram 1Mb |
||
| 60 | | CE1 = M2CC # M2D1 || enable ram 128Kb |
||
| 61 | | OEL = MLCC || enable internal ram 1Mb data bus for cpu access |
||
| 62 | | OEH = MHCC || enable internal ram 1Mb data bus for cpu access |
||
| 63 | | BE0 = DMA' & OE0' & ATA0' & FDC || ata0 data bus to 1Mb ram |
||
| 64 | | BE1 = DMA' & OE0' & ATA0 & FDC || ata1 data bus to 1Mb ram |
||
| 65 | | EV = DMA' & OE1' & FDC' & ALT' & MA0' || fdc data bus to even 1Mb |
||
| 66 | | ODD = DMA' & OE1' & FDC' & ALT' & MA0 || fdc data bus to odd 1Mb |
||
| 67 | | AEN = DMA' || cpu address enable |