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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 1 | - | 1 | || FILE: #0166.PLD |
| 2 | || PROJ: 20170501 |
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| 3 | || FD-02 FDC/ATA/DMA BOARD |
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| 4 | || |
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| 5 | || PART: G22V10-#0050 |
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| 6 | || |
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| 7 | || DEV : GAL22V10 |
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| 8 | || |
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| 9 | || DESC: RAM ACCESS CONTROL |
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| 10 | || |
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| 11 | | |
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| 12 | |GAL22V10 |
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| 13 | | |
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| 14 | || input signal description |
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| 15 | || GEN = gate enable |
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| 16 | || /DMA = dma enable |
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| 17 | || DIR = dma data bus direction (1 => read, 0 => write) |
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| 18 | || /S1M = enable 1Mb ram bank (otherwise 128k) |
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| 19 | || ATA = dma ata port select (0 => port 0, 1 => port 1) |
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| 20 | || /FDC = enable dma for fdc operation (otherwise ata) |
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| 21 | || /ALT = enable dma1 to use 1Mb ram bank (otherwise use 128Kb) |
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| 22 | || |
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| 23 | || INPUT |
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| 24 | | 1:MA0, 2:CX2, 3:GEN, 4:OE0, 5:OE1, 6:DMA, 7:RW, 8:DIR, |
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| 25 | | 9:S1M, 10:ATA, 11:FDC, 13:ALT, |
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| 26 | || OUTPUT |
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| 27 | | 14:CEL, 15:CEH, 16:CER, 17:ENL, 18:ENH, 19:BE0, |
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| 28 | | 20:BE1, 21:MDIR, 22:AEN, 23:A16E |
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| 29 | | |
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| 30 | | ACTIVE-LOW: CEL, CEH, CER, ENL, ENH, BE0, BE1, A16E |
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| 31 | | |
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| 32 | | |
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| 33 | | SIGNATURE: "0166 " |
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| 34 | | |
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| 35 | || -------------------------------------------------------- |
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| 36 | || common signals when dma disabled (DMA = 1 => cpu access) |
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| 37 | || |
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| 38 | | RAM0 = CX2' & DMA & OE0 || cpu access ram (dma0 = off) |
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| 39 | | RAM1 = CX2' & DMA & OE1 || cpu access ram (dma1 = off) |
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| 40 | | MLC0 = RAM0 & S1M' & MA0' || cpu access 1Mb even ram |
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| 41 | | MLC1 = RAM1 & S1M' & MA0' || cpu access 1Mb even ram |
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| 42 | | MHC0 = RAM0 & S1M' & MA0 || cpu access 1Mb odd ram |
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| 43 | | MHC1 = RAM1 & S1M' & MA0 || cpu access 1Mb odd ram |
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| 44 | | MLCA = MLC0 # MLC1 || cpu access 1Mb even ram |
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| 45 | | MHCA = MHC0 # MHC1 || cpu access 1Mb odd ram |
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| 46 | | MLCS = MLCA & GEN || cpu select 1Mb even ram |
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| 47 | | MHCS = MHCA & GEN || cpu select 1Mb odd ram |
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| 48 | | MMC0 = RAM0 & S1M || cpu access 128Kb ram |
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| 49 | | MMC1 = RAM1 & S1M || cpu access 128Kb ram |
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| 50 | | MMCS = (MMC0 # MMC1) & GEN || cpu select 128Kb ram |
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| 51 | || |
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| 52 | | CDIR = RW & DMA & OE0 & OE1 || cpu bus direction to 1Mb ram |
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| 53 | || |
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| 54 | || common signals when dma enabled (DMA = 0) |
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| 55 | | D0ON = DMA' & OE0' & OE1 & FDC || dma0 master |
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| 56 | | D1ON = DMA' & OE0 & OE1' & FDC' || dma1 master |
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| 57 | | D1MB = D1ON & ALT' || dma1 access 1Mb ram |
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| 58 | | D1MBL = D1MB & MA0' || dma1 access 1Mb even ram |
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| 59 | | D1MBH = D1MB & MA0 || dma1 access 1Mb odd ram |
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| 60 | | D128K = D1ON & ALT || dma1 access 128kb ram |
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| 61 | || |
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| 62 | | D0DIR = DIR & DMA' & FDC || dma0 bus direction to 1Mb ram |
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| 63 | | D1DIR = DIR' & DMA' & FDC' || dma1 bus direction to 1Mb ram |
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| 64 | || |
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| 65 | || output signals |
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| 66 | | CEL = MLCS # D0ON # D1MB || select even ram 1Mb |
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| 67 | | CEH = MHCS # D0ON # D1MB || select odd ram 1Mb |
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| 68 | | CER = MMCS # D128K || select ram 128Kb |
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| 69 | | ENL = MLCA # D1MBL || data bus to 1Mb even ram |
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| 70 | | ENH = MHCA # D1MBH || data bus to 1Mb even ram |
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| 71 | | BE0 = D0ON & ATA' || ata0 data bus to 1Mb ram |
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| 72 | | BE1 = D0ON & ATA || ata1 data bus to 1Mb ram |
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| 73 | | AEN = DMA' || cpu address enable |
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| 74 | | A16E = D1ON || enable extern A16 line for dma1 |
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| 75 | | MDIR = CDIR # D0DIR # D1DIR || bus direction to 1Mb ram |