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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 1 | - | 1 | || FILE: #0165.PLD |
| 2 | || PROJ: 20170501 |
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| 3 | || FD-02 FDC/ATA/DMA BOARD |
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| 4 | || |
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| 5 | || PART: G26CV12-#0165 |
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| 6 | || |
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| 7 | || DEV : GAL26CV12 |
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| 8 | || |
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| 9 | || DESC: DECODER I/O |
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| 10 | || |
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| 11 | | |
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| 12 | |GAL26CV12 |
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| 13 | | |
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| 14 | || INPUT |
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| 15 | | 1:A1, 2:A2, 3:A3, 4:A4, 5:A5, 6:A6, 8:IO, 9:RW, 10:PHI2, |
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| 16 | | 11:CX2, 12:FDC, 13:PHI0, 14:DMAE, 28:MW0, |
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| 17 | || OUTPUT |
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| 18 | | 15:CS0, 16:CS1, 17:CS2, 18:CS3, 19:CS4, 20:DBE, 22:GDD, 23:CS5, |
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| 19 | | 24:RD, 25:WE, 26:IOR, 27:IOW |
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| 20 | | |
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| 21 | | ACTIVE-LOW: CS0, CS1, CS2, CS3, DBE, GDD, CS5, RD, WE, IOR, IOW |
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| 22 | | |
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| 23 | | |
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| 24 | | SIGNATURE: "0165 " |
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| 25 | | |
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| 26 | || -------------------------------------------------------- |
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| 27 | || common signals when dma disbled (DMAE = 1 => cpu access) |
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| 28 | || |
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| 29 | | SCX2 = CX2' & DMAE || ram select when cpu access |
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| 30 | | SFDC = FDC' & DMAE || fdc select FD58-FD5F |
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| 31 | | DMA0 = IO' & A6' & A5' & A4' & DMAE || dma0 select FD80-FD8F |
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| 32 | | DMA1 = IO' & A6' & A5' & A4 & DMAE || dma1 select FD90-FD9F |
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| 33 | | ATA0 = IO' & A6' & A5 & A4' & DMAE || ata0 select FDA0-FDAF |
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| 34 | | ATA1 = IO' & A6' & A5 & A4 & DMAE || ata1 select FDB0-FDBF |
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| 35 | | VIA = IO' & A6 & A5' & A4' || via select FDC0-FDCF (always) |
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| 36 | || usb host CH376/CH375 select FDD0-FDD1 (always) |
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| 37 | | USB = IO' & A6 & A5' & A4 & A3' & A2' & A1' |
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| 38 | || |
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| 39 | | FDCR = SFDC & RW & PHI2 || cpu read fdc 02 sync |
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| 40 | | FDCW0 = SFDC & RW' & PHI2 & MW0' || cpu write fdc 02 sync |
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| 41 | | FDCW1 = SFDC & RW' & PHI0 & MW0 || cpu write fdc 00 sync |
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| 42 | | DM0R = DMA0 & RW & PHI2 || cpu read dma0 02 sync |
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| 43 | | DM0W0 = DMA0 & RW' & PHI2 & MW0' || cpu write dma0 02 sync |
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| 44 | | DM0W1 = DMA0 & RW' & PHI0 & MW0 || cpu write dma0 00 sync |
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| 45 | | DM1R = DMA1 & RW & PHI2 || cpu read dma1 02 sync |
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| 46 | | DM1W0 = DMA1 & RW' & PHI2 & MW0' || cpu write dma1 02 sync |
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| 47 | | DM1W1 = DMA1 & RW' & PHI0 & MW0 || cpu write dma1 00 sync |
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| 48 | | IORD = FDCR # DM0R # DM1R || cpu access to fdc, dma0, dma1 |
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| 49 | | IOWE = FDCW0 # FDCW1 # DM0W0 # DM0W1 # DM1W0 # DM1W1 |
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| 50 | | USBR = USB & RW & PHI2 || cpu read usb 02 sync |
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| 51 | | USBW0 = USB & RW' & PHI2 & MW0' || cpu write usb 02 sync |
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| 52 | | USBW1 = USB & RW' & PHI0 & MW0 || cpu write usb 00 sync |
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| 53 | || |
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| 54 | || global data bus enable for cpu access |
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| 55 | | BUSEN = SCX2 # SFDC # DMA0 # DMA1 # ATA0 # ATA1 # VIA # USB |
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| 56 | || |
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| 57 | || local shared dma data bus enable for cpu access |
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| 58 | | LBUSE = SCX2 # SFDC # DMA0 # DMA1 # ATA0 # ATA1 |
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| 59 | || |
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| 60 | || output signals |
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| 61 | | CS0 = DMA0 || dma0 FD80-FD8F |
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| 62 | | CS1 = DMA1 || dma1 FD90-FD9F |
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| 63 | | CS2 = VIA || via FDC0-FDCF |
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| 64 | | CS3 = SFDC || fdc FD58-FD5F |
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| 65 | | CS4 = SFDC || fdc FD58-FD5F (positive) |
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| 66 | | CS5 = USB || usb FDD0-FDD1 |
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| 67 | | RD = USBR || usb read strobe |
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| 68 | | WE = USBW0 # USBW1 || usb write strobe |
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| 69 | | IOR = DMAE ?? IORD || i/o read strobe 3-states |
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| 70 | | IOW = DMAE ?? IOWE || i/o write strobe 3-states |
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| 71 | | DBE = BUSEN & PHI2 || global data bus enable |
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| 72 | | GDD = LBUSE || local data bus enable |