Details | Last modification | View Log | RSS feed
| Rev | Author | Line No. | Line |
|---|---|---|---|
| 1 | - | 1 | || FILE: #0165.PLD |
| 2 | || PROJ: 20170501 |
||
| 3 | || FD-02 FDC/ATA/DMA BOARD |
||
| 4 | || |
||
| 5 | || PART: G26CV12-#0165 |
||
| 6 | || |
||
| 7 | || DEV : GAL26CV12 |
||
| 8 | || |
||
| 9 | || DESC: DECODER I/O |
||
| 10 | || |
||
| 11 | | |
||
| 12 | |GAL26CV12 |
||
| 13 | | |
||
| 14 | || GEN = gate enable |
||
| 15 | || /MGE = ram gate enable (/OE0 nor /OE 1) |
||
| 16 | || INPUT |
||
| 17 | | 1:A1, 2:-, 3:A3, 4:A4, 5:A5, 6:A6, 8:IO, 9:RW, 10:PHI2, |
||
| 18 | | 11:CX2, 12:MGE, 13:PHI0, 14:DMA, 28:GEN, |
||
| 19 | || OUTPUT |
||
| 20 | | 15:CE0, 16:CE1, 17:AT0, 18:AT1, 19:CE2, 20:DBE, 22:DDE, 23:CE3, |
||
| 21 | | 24:MRD, 25:MWE, 26:IOR, 27:IOW |
||
| 22 | | |
||
| 23 | | ACTIVE-LOW: CE0, CE1, AT0, AT1, CE2, DBE, DDE, MRD, MWE, IOR, IOW |
||
| 24 | | |
||
| 25 | | |
||
| 26 | | SIGNATURE: "0165B " |
||
| 27 | | |
||
| 28 | || -------------------------------------------------------- |
||
| 29 | || common signals when dma disbled (DMAE = 1 => cpu access) |
||
| 30 | || |
||
| 31 | | SCX2 = CX2' & DMA || ram select when cpu access |
||
| 32 | | FDD0 = IO' & A6 & A5' & A4 || select FDD0-FDDF |
||
| 33 | | FDC = FDD0 & A3 & DMA || fdc select FDD8-FDDF |
||
| 34 | | DM0 = IO' & A6' & A5' & A4' & DMA || dma0 select FD80-FD8F |
||
| 35 | | DM1 = IO' & A6' & A5' & A4 & DMA || dma1 select FD90-FD9F |
||
| 36 | | ATA0 = IO' & A6' & A5 & A4' & DMA || ata0 select FDA0-FDAF |
||
| 37 | | ATA1 = IO' & A6' & A5 & A4 & DMA || ata1 select FDB0-FDBF |
||
| 38 | || VIA = IO' & A6 & A5' & A4' || via select FDC0-FDCF (always) |
||
| 39 | || USB = FDD0 & A3' & A2' & A1' || usb select FDD0-FDD1 (always) |
||
| 40 | || |
||
| 41 | | FDCR = FDC & RW & GEN || cpu read fdc 02 sync |
||
| 42 | | FDCW = FDC & RW' & PHI2 || cpu write fdc 02 sync |
||
| 43 | | DM0R = DM0 & RW & GEN || cpu read dma0 02 sync |
||
| 44 | | DM0W = DM0 & RW' & PHI2 || cpu write dma0 00 sync |
||
| 45 | | DM1R = DM1 & RW & GEN || cpu read dma1 02 sync |
||
| 46 | | DM1W = DM1 & RW' & PHI2 || cpu write dma1 00 sync |
||
| 47 | | IORD = FDCR # DM0R # DM1R || cpu read fdc, dma0, dma1 |
||
| 48 | | IOWE = FDCW # DM0W # DM1W || cpu write fdc, dma0, dma1 |
||
| 49 | || |
||
| 50 | | MEMR = SCX2 & MGE' & RW & PHI2 || cpu read ram |
||
| 51 | | MEMW = SCX2 & MGE' & RW' & PHI0 || cpu write ram (00 sync) |
||
| 52 | || |
||
| 53 | || global data bus enable for cpu access |
||
| 54 | || DBEE = SCX2 # FDC # DM0 # DM1 # ATA0 # ATA1 # VIA # USB |
||
| 55 | | DBEE = SCX2 # IO' |
||
| 56 | |||
| 57 | || |
||
| 58 | || local shared dma data bus enable for cpu access |
||
| 59 | | DDEE = SCX2 # FDC # DM0 # DM1 # ATA0 # ATA1 |
||
| 60 | || |
||
| 61 | || output signals |
||
| 62 | | CE0 = DM0 || dma0 FD80-FD8F |
||
| 63 | | CE1 = DM1 || dma1 FD90-FD9F |
||
| 64 | | AT0 = ATA0 || ata0 FDA0-FDAF |
||
| 65 | | AT1 = ATA1 || ata1 FDA0-FDAF |
||
| 66 | | CE2 = FDC || fdc FDD8-FDDF |
||
| 67 | | CE3 = FDC || fdc FDD8-FDDF (positive) |
||
| 68 | | IOR = DMA ?? IORD || i/o read strobe 3-states |
||
| 69 | | IOW = DMA ?? IOWE || i/o write strobe 3-states |
||
| 70 | | MWE = DMA ?? MEMW || write ram strobe 3-states |
||
| 71 | | MRD = DMA ?? MEMR || read ram strobe 3-states |
||
| 72 | || DBE = DBEE & GEN || global data bus enable |
||
| 73 | || DDE = DDEE & GEN || local data bus enable |
||
| 74 | | DBE = DBEE || global data bus enable |
||
| 75 | | DDE = DDEE || local data bus enable |