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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 1 | - | 1 | || FILE: #0165.PLD |
| 2 | || PROJ: 20170501 |
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| 3 | || FD-02 FDC/ATA/DMA BOARD |
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| 4 | || |
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| 5 | || PART: G26CV12-#0165 |
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| 6 | || |
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| 7 | || DEV : GAL26CV12 |
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| 8 | || |
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| 9 | || DESC: DECODER I/O |
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| 10 | || |
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| 11 | | |
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| 12 | |GAL26CV12 |
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| 13 | | |
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| 14 | || GEN = gate enable |
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| 15 | || /MGE = ram gate enable (/OE0 nor /OE 1) |
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| 16 | || INPUT |
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| 17 | | 1:A1, 2:-, 3:A3, 4:A4, 5:A5, 6:A6, 8:IO, 9:RW, 10:PHI2, |
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| 18 | | 11:CX2, 12:MGE, 13:PHI0, 14:DMA, 28:GEN, |
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| 19 | || OUTPUT |
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| 20 | | 15:CE0, 16:CE1, 17:AT0, 18:AT1, 19:CE2, 20:DBE, 22:DDE, 23:CE3, |
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| 21 | | 24:MRD, 25:MWE, 26:IOR, 27:IOW |
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| 22 | | |
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| 23 | | ACTIVE-LOW: CE0, CE1, AT0, AT1, CE2, DBE, DDE, MRD, MWE, IOR, IOW |
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| 24 | | |
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| 25 | | |
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| 26 | | SIGNATURE: "0165 " |
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| 27 | | |
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| 28 | || -------------------------------------------------------- |
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| 29 | || common signals when dma disbled (DMAE = 1 => cpu access) |
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| 30 | || |
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| 31 | | SCX2 = CX2' & DMA || ram select when cpu access |
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| 32 | | FDD0 = IO' & A6 & A5' & A4 || select FDD0-FDDF |
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| 33 | | FDC = FDD0 & A3 & DMA || fdc select FDD8-FDDF |
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| 34 | | DM0 = IO' & A6' & A5' & A4' & DMA || dma0 select FD80-FD8F |
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| 35 | | DM1 = IO' & A6' & A5' & A4 & DMA || dma1 select FD90-FD9F |
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| 36 | | ATA0 = IO' & A6' & A5 & A4' & DMA || ata0 select FDA0-FDAF |
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| 37 | | ATA1 = IO' & A6' & A5 & A4 & DMA || ata1 select FDB0-FDBF |
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| 38 | || VIA = IO' & A6 & A5' & A4' || via select FDC0-FDCF (always) |
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| 39 | || USB = FDD0 & A3' & A2' & A1' || usb select FDD0-FDD1 (always) |
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| 40 | || |
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| 41 | | FDCR = FDC & RW & GEN || cpu read fdc 02 sync |
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| 42 | | FDCW = FDC & RW' & PHI0 || cpu write fdc 00 sync |
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| 43 | | DM0R = DM0 & RW & PHI2 || cpu read dma0 02 sync |
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| 44 | | DM0W = DM0 & RW' & PHI0 || cpu write dma0 00 sync |
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| 45 | | DM1R = DM1 & RW & PHI2 || cpu read dma1 02 sync |
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| 46 | | DM1W = DM1 & RW' & PHI0 || cpu write dma1 00 sync |
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| 47 | | IORD = FDCR # DM0R # DM1R || cpu read fdc, dma0, dma1 |
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| 48 | | IOWE = FDCW # DM0W # DM1W || cpu write fdc, dma0, dma1 |
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| 49 | || |
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| 50 | | MEMR = SCX2 & MGE' & RW & PHI2 || cpu read ram |
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| 51 | | MEMW = SCX2 & MGE' & RW' & PHI0 || cpu write ram (00 sync) |
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| 52 | || |
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| 53 | || global data bus enable for cpu access |
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| 54 | || DBEE = SCX2 # FDC # DM0 # DM1 # ATA0 # ATA1 # VIA # USB |
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| 55 | | DBEE = SCX2 # IO' |
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| 56 | |||
| 57 | || |
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| 58 | || local shared dma data bus enable for cpu access |
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| 59 | | DDEE = SCX2 # FDC # DM0 # DM1 # ATA0 # ATA1 |
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| 60 | || |
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| 61 | || output signals |
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| 62 | | CE0 = DM0 || dma0 FD80-FD8F |
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| 63 | | CE1 = DM1 || dma1 FD90-FD9F |
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| 64 | | AT0 = ATA0 || ata0 FDA0-FDAF |
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| 65 | | AT1 = ATA1 || ata1 FDA0-FDAF |
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| 66 | | CE2 = FDC || fdc FDD8-FDDF |
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| 67 | | CE3 = FDC || fdc FDD8-FDDF (positive) |
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| 68 | | IOR = DMA ?? IORD || i/o read strobe 3-states |
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| 69 | | IOW = DMA ?? IOWE || i/o write strobe 3-states |
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| 70 | | MWE = DMA ?? MEMW || write ram strobe 3-states |
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| 71 | | MRD = DMA ?? MEMR || read ram strobe 3-states |
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| 72 | | DBE = DBEE & GEN || global data bus enable |
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| 73 | | DDE = DDEE & GEN || local data bus enable |