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||	FILE:	#0050.PLD
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||	PROJ:	20120601
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||	PART:	G22V10-#0050
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||
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||	DEV :	GAL22V10
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||
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|| 	DESC:	MASTER CLOCK
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||
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|
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|GAL22V10
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|
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|| INPUT
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|  1:CLK, 2:PD, 3:F2, 4:S0, 5:VPA, 6:VDA, 7:RES, 8:P2IN, 9:P1IN, 10:P0IN,
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|  11:P4IN, 13:RDY,
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|| OUTPUT
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|  14:P2O, 15:Q0, 16:Q1, 17:Q2, 18:VMA, 19:ALE, 20:GOE,
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|  21:PHI1, 22:PHI0, 23:P4O
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|
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| ACTIVE-LOW: VMA
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|
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| SIGNATURE: "0050    "
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|
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|| P2O -> CLOCK 02 CPU
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|| CONNETTERE P0IN CON PHI0
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|| CONNETTERE P1IN CON PHI1
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|| CONNETTERE P4IN CON P4O
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||
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|| Q0 = 8M, Q1 = 4M, Q2 = 2M
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|  Q[2..0] = CLK // Q[2..0] + 1
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|  A = Q2 & F2'		|| 2MHz
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|  B = Q1 & F2		|| 4MHz
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|  PHI0 = (A # B)	|| FASE 0
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|  P4O = P0IN		|| FASE 0 RITARDATA
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|| P0IN -> FASE 0 RITARDO T  (PD = 1)
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|| P4IN -> FASE 0 RITARDO 2T (PD = 0)
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|  P2O = ((P0IN & PD) # (P4IN & PD'))
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|  PHI1 = P2IN'		|| FASE 1 RITARDATA RISPETTO A PHI2
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|  VMA  = ((VDA & RES) # (VPA & RES))
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|  ALE    = (RDY & P0IN' & P2IN')
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|  DBEA   = (RDY & P2IN' & S0)
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|  DBEB   = (RDY & P1IN  & S0')
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|  GOE    = (DBEA # DBEB)