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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 1 | - | 1 | || FILE: #0000.PLD |
| 2 | || PROJ: 20120607 |
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| 3 | || PART: G26CV12-#0000 |
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| 4 | || |
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| 5 | || DEV : GAL26CV12 |
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| 6 | || |
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| 7 | || DESC: CONTROLLER DMA/FDC |
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| 8 | || |
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| 9 | | |
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| 10 | |GAL26CV12 |
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| 11 | | |
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| 12 | || INPUT |
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| 13 | | 1:PHI2, 2:RW, 3:PHI0, 4:CX2, 5:DMA, 6:FDC, 8:WD, 9:WF, 10:MW0, |
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| 14 | | 11:AEN, 12:OE, 13:EN, 14:RDY, 28:-, |
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| 15 | || OUTPUT |
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| 16 | | 15:DBE, 16:CS0, 17:CS1, 18:CS2, 19:IOR, 20:IOW, 22:MRD, 23:MWE, |
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| 17 | | 24:CS3, 25:J, 26:PHI2N, 27:K |
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| 18 | | |
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| 19 | | ACTIVE-LOW: DBE, CS0, CS1, IOR, IOW, MRD, MWE, CS3, J, PHI2N |
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| 20 | | |
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| 21 | | |
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| 22 | | SIGNATURE: "0000 " |
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| 23 | | |
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| 24 | || -------------------------------------------------------- |
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| 25 | || SEGNALI COMANDO FLIP-FLOP WAIT |
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| 26 | | PHI2N = PHI2 |
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| 27 | || ABILITAZIONE WAIT |
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| 28 | | WTX = ((DMA' & WD') # (FDC' & WF')) |
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| 29 | || COMANDO J,K |
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| 30 | | DATA = (RDY # WTX') |
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| 31 | | J = DATA |
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| 32 | | K = DATA |
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| 33 | || |
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| 34 | || -------------------------------------------------------- |
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| 35 | || CHIP SELECT RAM, DMA & FDC VALIDI SOLO SE AEN = 0 |
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| 36 | | DMAA = (DMA' & AEN') |
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| 37 | | FDCA = (FDC' & AEN') |
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| 38 | | CX2A = (CX2' & AEN') |
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| 39 | | CS0 = DMAA |
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| 40 | | CS1 = FDCA |
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| 41 | | CS2 = FDCA |
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| 42 | || |
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| 43 | || -------------------------------------------------------- |
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| 44 | || SEGNALI UM8388 RD, WR (FDC) |
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| 45 | || RD, WR SINCRONIZZATI CON PHI2 (WF = 1) |
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| 46 | | UMR1 = (FDCA & WF & RW & PHI2) |
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| 47 | | UMW1 = (FDCA & WF & RW' & PHI2) |
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| 48 | || RD, WR SINCRONIZZATI CON EN (WF = 0) |
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| 49 | | UMR2 = (FDCA & WF' & RW & EN) |
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| 50 | | UMW2 = (FDCA & WF' & RW' & EN) |
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| 51 | | UMRD = (UMR1 # UMR2) |
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| 52 | | UMWE = (UMW1 # UMW2) |
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| 53 | || |
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| 54 | || -------------------------------------------------------- |
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| 55 | || SEGNALI 82C37 RD, WR (DMA) |
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| 56 | || RD, WR SINCRONIZZATI CON PHI2 (WD = 1) |
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| 57 | | DMR1 = (DMAA & WD & RW & PHI2) |
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| 58 | | DMW1 = (DMAA & WD & RW' & PHI2) |
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| 59 | || RD, WR SINCRONIZZATI CON EN (WD = 0) |
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| 60 | | DMR2 = (DMAA & WD' & RW & EN) |
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| 61 | | DMW2 = (DMAA & WD' & RW' & EN) |
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| 62 | | DMRD = (DMR1 # DMR2) |
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| 63 | | DMWE = (DMW1 # DMW2) |
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| 64 | || |
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| 65 | || -------------------------------------------------------- |
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| 66 | || SEGNALI RD,WR,MRD,MWR 3 STATI PER DMA |
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| 67 | || XAE attiva uscita 3-stati se LOW |
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| 68 | | IORD = (DMRD # UMRD) |
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| 69 | | IOWR = (DMWE # UMWE) |
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| 70 | | MEMRD = (CX2' & RW & PHI2 & OE) |
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| 71 | | MEMWRA = (CX2' & RW' & PHI2 & MW0 & OE) |
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| 72 | | MEMWRB = (CX2' & RW' & PHI0 & MW0' & OE) |
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| 73 | | MEMWR = (MEMWRA # MEMWRB) |
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| 74 | | IOR = AEN' ?? IORD |
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| 75 | | IOW = AEN' ?? IOWR |
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| 76 | | MRD = AEN' ?? MEMRD |
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| 77 | | MWE = AEN' ?? MEMWR |
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| 78 | || -------------------------------------------------------- |
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| 79 | || SELEZIONE SHARED RAM |
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| 80 | || DMA ATTIVO - RAM SEMPRE SELEZIONATA |
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| 81 | | CEA = (OE') |
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| 82 | || DMA INATTIVO |
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| 83 | | CEB = (CX2' & OE & PHI2) |
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| 84 | | CS3 = (CEA # CEB) |
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| 85 | || |
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| 86 | || -------------------------------------------------------- |
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| 87 | || ABILITAZIONE BUFFER DATI BUS DMA |
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| 88 | | FDCZ1 = (FDCA & WF & PHI2) |
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| 89 | | FDCZ2 = (FDCA & WF' & EN) |
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| 90 | | DMAZ1 = (DMAA & WD & PHI2) |
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| 91 | | DMAZ2 = (DMAA & WD' & EN) |
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| 92 | | DBE = (FDCZ1 # FDCZ2 # DMAZ1 # DMAZ2 # (CX2A & PHI2)) |