Subversion Repositories MB01 Project

Rev

Details | Last modification | View Log | RSS feed

Rev Author Line No. Line
1 - 1
OrCAD LOGIC COMPILER  v2.01 N 12/09/94  (Source file .\PLD\#9001.PLD)
2
 
3
  1  ||	FILE:	#9001.PLD
4
  2  ||	PROJ:	20130517
5
  3  ||	PART:	G26CV12-#9001
6
  4  ||
7
  5  ||	DEV :	GAL26CV12
8
  6  ||
9
  7  || 	DESC:	VIDEO CONTROL
10
  8  ||
11
  9  |
12
 10  |GAL26CV12
13
 11  |
14
 12  || INPUT
15
 13  |  1:CLK, 2:LD, 3:CEI, 4:DEI, 5:HSI, 6:VSI, 8:AT5, 9:CT0, 10:CT1,
16
 14  | 11:CT2, 12:CT3, 13:CT6, 14:CT7, 15:D0, 27:F1, 28:F2,
17
 15  || OUTPUT
18
 16  |  26:HS, 25:VS, 24:EUL, 23:CE, 22:DE, 20:FB, 19:FC,
19
 17  |  18:Q0, 17:PS5, 16:-
20
 18  |
21
 19  | SIGNATURE: "9001    "
22
 20  |
23
 21  || --------------------------------------------------------
24
 22  |  B0  = (D0  & LD') # (Q0  & LD)
25
 23  |  HSD = (HSI & LD') # (HS  & LD)
26
 24  |  VSD = (VSI & LD') # (VS  & LD)
27
 25  |  CED = (CEI & LD') # (CE  & LD)
28
 26  || /CT7 ABILITA DISPLAY ENABLE
29
 27  |  DED = (DEI & LD' & CT7') # (DE  & LD)
30
 28  || CT6 ABILITA ATTRIBUTO AT5 = UNDER LINE
31
 29  |  ULD = (AT5 & LD' & CT6) # (EUL  & LD)
32
 30  || /CT6 ABILITA ATTRIBUTO AT5 = PALETTE ADDRESS PS5
33
 31  |  PS5 = (AT5 & CT6')
34
 32  || FREQUENZA BLINK CARATTERE (1/32 VSYNC)
35
 33  || CT3 INVERTE FREQUENZA
36
 34  |  FBD = (CT3' & LD' & F2) # (CT3 & LD' & F2') # (LD & FB)
37
 35  || FREQUENZA BLINK CURSORE
38
 36  || /CT0 -> 1/16 VSYNC -- CT0 -> 1/32 VSYNC
39
 37  || CT1  -> INVERTE FREQUENZA BLINK CURSORE
40
 38  || CT2  -> ABILITA BLINK CURSORE
41
 39  || CT2 = 0 => CURSORE FISSO (se abilitato da CRTC)
42
 40  |  FL0 = (CT2 & F1' & LD' & F2'  & CT1)
43
 41  |  FL1 = (CT2 & F1' & LD' & CT0' & CT1)
44
 42  |  FL2 = (CT2 & F1  & LD' & CT0' & CT1')
45
 43  |  FL3 = (CT2 & LD' & F2' & CT0  & CT1)
46
 44  |  FL4 = (CT2 & LD' & F2  & CT0  & CT1')
47
 45  |  FL5 = (LD & FC)
48
 46  |  FL6 = (CT2' & LD')
49
 47  |  FCD = (FL0 # FL1 # FL2 # FL3 # FL4 # FL5 # FL6)
50
 48  || LOAD DATA
51
 49  |  Q0  = CLK // B0
52
 50  |  HS  = CLK // HSD
53
 51  |  VS  = CLK // VSD
54
 52  |  CE  = CLK // CED
55
 53  |  DE  = CLK // DED
56
 54  |  EUL = CLK // ULD
57
 55  |  FB  = CLK // FBD
58
 
59
 
60
61
 
62
 
63
 
64
65
I202  5/31/13  6:38 pm  (Friday)
66
 
67
 
68
OrCAD DEVICE FITTER  v2.01   12/09/94  (Source file .\PLD\#9001.PLA)
69
70
71
 
72
RESOLVED EXPRESSIONS (Reduction 0)
73
 
74
 
75
 
76
 
77
78
 
79
                  87   LD  Q0
80
 
81
HS                11   LD' HSI
82
 
83
84
VS                20   LD' VSI
85
 
86
87
CE                38   LD' CEI
88
 
89
90
DE                49   LD' DEI  CT7'
91
 
92
93
EUL               29   LD' AT5  CT6
94
 
95
96
FB                62   LD' CT3' F2
97
 
98
                  64   LD  FB
99
100
 
101
                  76   LD' CT0' CT1  CT2  F1'
102
                  77   LD' CT0  CT1' CT2  F2
103
                  78   LD' CT0  CT1  CT2  F2'
104
 
105
                  80   LD' CT2'
106
                  81   LD  FC
107
108
109
110
SIGNAL ASSIGNMENT
111
                                      Rows
112
 
113
 
114
 
115
 
116
  2.     LD              4        -    -    -        High
117
  3.     CEI             8        -    -    -        High
118
  4.     DEI            12        -    -    -        High
119
  5.     HSI            16        -    -    -        High
120
 
121
  8.     AT5            24        -    -    -        High
122
  9.     CT0            28        -    -    -        High
123
 10.     CT1            32        -    -    -        High
124
 11.     CT2            36        -    -    -        High
125
 12.     CT3            40        -    -    -        High
126
 13.     CT6            44        -    -    -        High
127
 14.     CT7            48        -    -    -        High
128
 15.     D0             50      112    9    0        High    (Registered)
129
 16.     -              46      103    9    0                (Three-state)
130
 17.     PS5            42       94    9    1        High    (Three-state)
131
 18.     Q0             39       85    9    2        High    (Registered)
132
 19.     FC             35       74   11    7        High    (Registered)
133
 20.     FB             31       61   13    3        High    (Registered)
134
 22.     DE             27       48   13    2        High    (Registered)
135
 23.     CE             23       37   11    2        High    (Registered)
136
 24.     EUL            19       28    9    2        High    (Registered)
137
 25.     VS             15       19    9    2        High    (Registered)
138
 26.     HS             11       10    9    2        High    (Registered)
139
 27.     F1              6        1    9    0        High    (Registered)
140
 28.     F2              2        -    -    -        High
141
 29.     -               -        0    1    0
142
 30.     -               -      121    1    0
143
                                    ---- ----
144
                                     122   23  (19%)
145
146
147
I200  No fatal errors found in source code (device phase).
148
I201  No warnings.
149
150
151
 
152
 
153
*
154
QP28* QF6432* QV1024*
155
 
156
 
157
 
158
L0624 1111011111101111111111111111111111111111111111111111*
159
L0988 1111111111111111111111111111111111111111111111111111*
160
L1040 1111101111111111111101111111111111111111111111111111*
161
L1092 1111011111111110111111111111111111111111111111111111*
162
L1456 1111111111111111111111111111111111111111111111111111*
163
L1508 1111101111111111111111110111111111111111111101111111*
164
L1560 1111011111111111111011111111111111111111111111111111*
165
L1924 1111111111111111111111111111111111111111111111111111*
166
L1976 1111101101111111111111111111111111111111111111111111*
167
L2028 1111011111111111111111101111111111111111111111111111*
168
L2496 1111111111111111111111111111111111111111111111111111*
169
L2548 1111101111110111111111111111111111111111111111111011*
170
L2600 1111011111111111111111111110111111111111111111111111*
171
L3172 1111111111111111111111111111111111111111111111111111*
172
L3224 1101101111111111111111111111111111111111101111111111*
173
L3276 1110101111111111111111111111111111111111011111111111*
174
L3328 1111011111111111111111111111111011111111111111111111*
175
L3848 1111111111111111111111111111111111111111111111111111*
176
L3900 1111100111111111111111111111101110110111111111111111*
177
L3952 1111101011111111111111111111101101110111111111111111*
178
L4004 1101101111111111111111111111011110110111111111111111*
179
L4056 1110101111111111111111111111011101110111111111111111*
180
L4108 1110101011111111111111111111111101110111111111111111*
181
L4160 1111101111111111111111111111111111111011111111111111*
182
L4212 1111011111111111111111111111111111101111111111111111*
183
L4420 1111111111111111111111111111111111111111111111111111*
184
L4472 1111101111111111111111111111111111111111111111111101*
185
L4524 1111011111111111111111111111111111111110111111111111*
186
L4888 1111111111111111111111111111111111111111111111111111*
187
L4940 1111111111111111111111110111111111111111111110111111*
188
L6344 1110101010101010101111110011100100110000001100000011*
189
L6396 000100100000001000000010000000100000*
190
CCCAC*
191
192
I202  5/31/13  6:38 pm  (Friday)
193
I203  Memory usage 9K
194
I204  Elapsed time 1 second
195