WebSVN – MB01 Project – Blame – /trunk/gal/20120607-MB01-FDC/PLD/#0001.LST

Rev	Author	Line No.	Line
1	-	1	OrCAD LOGIC COMPILER v2.01 N 12/09/94 (Source file .\PLD\#0001.PLD)
		2
		3	1 \|\| FILE: #0001.PLD
		4	2 \|\| PROJ: 20120607
		5	3 \|\| PART: G16V8-#0001
		6	4 \|\|
		7	5 \|\| DEV : GAL16V8
		8	6 \|\|
		9	7 \|\| DESC: DMA CONTROL
		10	8 \|\|
		11	9 \|
		12	10 \|GAL16V8A
		13	11 \|
		14	12 \|\| INPUT
		15	13 \| 1:DAEN, 2:HRQ, 3:EOP, 4:RES, 5:DME, 6:DMR, 7:FDR, 8:XTC, 9:-, 11:-,
		16	14 \|\| OUTPUT
		17	15 \| 12:OE, 13:DRS, 14:HLD, 15:XTCP, 16:FRS, 17:TC, 18:AEN, 19:AENN
		18	16 \|
		19	17 \| ACTIVE-LOW: OE, AENN
		20	18 \|
		21	19 \| PROPERTY:"SIMPLE"
		22	20 \|
		23	21 \| SIGNATURE: "0001 "
		24	22 \|
		25	23 \|\| --------------------------------------------------------
		26	24 \|\| /OE -> abilitazione output latch address 82C37
		27	25 \|\| AEN -> abilitazione buffer address CPU
		28	26 \|\| HLD -> abilitazione DMA 82C37
		29	27 \|\| DAEN <- da 82C37 - abilitazione latch address
		30	28 \|\| HRQ <- da 82C37 - richiesta DMA
		31	29 \|\| /DME <- abilitazione DMA da CPU
		32	30 \|\| AENX, HRQX -> attivi solo se DME LOW
		33	31 \| AENX = DAEN & DME'
		34	32 \| HRQX = HRQ & DME'
		35	33 \| OE = AENX
		36	34 \| HLD = HRQX
		37	35 \|\| AEN = (AENX # HRQX)
		38	36 \| AEN = (DME')
		39	37 \| AENN = (AENX # HRQX)
		40	38 \|\|
		41	39 \|\| DRS -> reset 82C37 (impulso positivo)
		42	40 \|\| attivo o per reset hardware o per comando /DMR da CPU
		43	41 \| DRS = ((RES') # (DMR)')
		44	42 \|\| FRS -> reset hardware per UM8388 (impulso positivo)
		45	43 \| FRS = ((RES') # (FDR)')
		46	44 \|\|
		47	45 \|\| XTCP - inversione TC esterno da CPU
		48	46 \| XTCP = XTC'
		49	47 \|\| TC -> terminal count per UM8388
		50	48 \| TC = EOP'
		51
		52
		53
		54	I201 No warnings.
		55
		56
		57
		58	I203 Memory usage 76K
		59	I204 Elapsed time 1 second
		60	OrCAD DEVICE FITTER v2.01 12/09/94 (Source file .\PLD\#0001.PLA)
		61
		62	I289 Simple GAL architecture selected.
		63
		64
		65
		66
		67
		68
		69
		70
		71
		72	1 HRQ DME'
		73
		74	HLD 40 HRQ DME'
		75
		76
		77
		78
		79	49 DMR'
		80
		81	FRS 24 RES'
		82	25 FDR'
		83
		84	XTCP 32 XTC'
		85
		86
		87
		88
		89
		90
		91
		92
		93
		94
		95	1. DAEN 2 - - - High (Clock)
		96	2. HRQ 0 - - - High
		97	3. EOP 4 - - - High
		98
		99	5. DME 12 - - - High
		100	6. DMR 16 - - - High
		101	7. FDR 20 - - - High
		102	8. XTC 24 - - - High
		103	9. - 28 - - -
		104	11. - 30 - - - (Enable)
		105	12. OE 27 56 8 1 Low
		106	13. DRS 22 48 8 2 High
		107	14. HLD 18 40 8 1 High
		108	15. XTCP 0 32 8 1 High
		109	16. FRS 0 24 8 2 High
		110	17. TC 14 16 8 1 High
		111	18. AEN 10 8 8 1 High
		112	19. AENN 7 0 8 2 Low
		113	---- ----
		114	64 11 (17%)
		115
		116
		117	I200 No fatal errors found in source code (device phase).
		118	I201 No warnings.
		119
		120
		121	OrCAD DEVICE
		122	Type: GAL16V8
		123
		124
		125
		126	L0000 11 01 11 11 11 11 10 11 11 11 11 11 11 11 11 11 *
		127	L0032 01 11 11 11 11 11 10 11 11 11 11 11 11 11 11 11 *
		128	L0256 11 11 11 11 11 11 10 11 11 11 11 11 11 11 11 11 *
		129	L0512 11 11 10 11 11 11 11 11 11 11 11 11 11 11 11 11 *
		130	L0768 11 11 11 11 10 11 11 11 11 11 11 11 11 11 11 11 *
		131	L0800 11 11 11 11 11 11 11 11 11 11 10 11 11 11 11 11 *
		132	L1024 11 11 11 11 11 11 11 11 11 11 11 11 10 11 11 11 *
		133	L1280 01 11 11 11 11 11 10 11 11 11 11 11 11 11 11 11 *
		134	L1536 11 11 11 11 10 11 11 11 11 11 11 11 11 11 11 11 *
		135	L1568 11 11 11 11 11 11 11 11 10 11 11 11 11 11 11 11 *
		136	L1792 11 01 11 11 11 11 10 11 11 11 11 11 11 11 11 11 *
		137	L2048 01 11 11 10 00 11 00 00 00 11 00 00 00 11 00 00 *
		138	L2080 00 11 00 01 00 10 00 00 00 10 00 00 00 10 00 00 *
		139	L2112 00 10 00 00 00 00 00 00 11 11 11 11 11 11 11 11 *
		140	L2144 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
		141	L2176 11 11 11 11 11 11 11 11 10 *
		142	C3419*
		143
		144	I202 9/6/12 11:03 am (Thursday)
		145	I203 Memory usage 5K
		146	I204 Elapsed time 1 second
		147

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