WebSVN – MB01 Project – Blame – /trunk/gal/20120607-MB01-FDC/PLD/#0000.LST

Rev	Author	Line No.	Line
1	-	1	OrCAD LOGIC COMPILER v2.01 N 12/09/94 (Source file .\PLD\#0000.PLD)
		2
		3	1 \|\| FILE: #0000.PLD
		4	2 \|\| PROJ: 20120607
		5	3 \|\| PART: G26CV12-#0000
		6	4 \|\|
		7	5 \|\| DEV : GAL26CV12
		8	6 \|\|
		9	7 \|\| DESC: CONTROLLER DMA/FDC
		10	8 \|\|
		11	9 \|
		12	10 \|GAL26CV12
		13	11 \|
		14	12 \|\| INPUT
		15	13 \| 1:PHI2, 2:RW, 3:PHI0, 4:CX2, 5:DMA, 6:FDC, 8:WD, 9:WF, 10:MW0,
		16	14 \| 11:AEN, 12:OE, 13:EN, 14:RDY, 28:-,
		17	15 \|\| OUTPUT
		18	16 \| 15:DBE, 16:CS0, 17:CS1, 18:CS2, 19:IOR, 20:IOW, 22:MRD, 23:MWE,
		19	17 \| 24:CS3, 25:J, 26:PHI2N, 27:K
		20	18 \|
		21	19 \| ACTIVE-LOW: DBE, CS0, CS1, IOR, IOW, MRD, MWE, CS3, J, PHI2N
		22	20 \|
		23	21 \|
		24	22 \| SIGNATURE: "0000 "
		25	23 \|
		26	24 \|\| --------------------------------------------------------
		27	25 \|\| SEGNALI COMANDO FLIP-FLOP WAIT
		28	26 \| PHI2N = PHI2
		29	27 \|\| ABILITAZIONE WAIT
		30	28 \| WTX = ((DMA' & WD') # (FDC' & WF'))
		31	29 \|\| COMANDO J,K
		32	30 \| DATA = (RDY # WTX')
		33	31 \| J = DATA
		34	32 \| K = DATA
		35	33 \|\|
		36	34 \|\| --------------------------------------------------------
		37	35 \|\| CHIP SELECT RAM, DMA & FDC VALIDI SOLO SE AEN = 0
		38	36 \| DMAA = (DMA' & AEN')
		39	37 \| FDCA = (FDC' & AEN')
		40	38 \| CX2A = (CX2' & AEN')
		41	39 \| CS0 = DMAA
		42	40 \| CS1 = FDCA
		43	41 \| CS2 = FDCA
		44	42 \|\|
		45	43 \|\| --------------------------------------------------------
		46	44 \|\| SEGNALI UM8388 RD, WR (FDC)
		47	45 \|\| RD, WR SINCRONIZZATI CON PHI2 (WF = 1)
		48	46 \| UMR1 = (FDCA & WF & RW & PHI2)
		49	47 \| UMW1 = (FDCA & WF & RW' & PHI2)
		50	48 \|\| RD, WR SINCRONIZZATI CON EN (WF = 0)
		51	49 \| UMR2 = (FDCA & WF' & RW & EN)
		52	50 \| UMW2 = (FDCA & WF' & RW' & EN)
		53	51 \| UMRD = (UMR1 # UMR2)
		54	52 \| UMWE = (UMW1 # UMW2)
		55	53 \|\|
		56	54 \|\| --------------------------------------------------------
		57	55 \|\| SEGNALI 82C37 RD, WR (DMA)
		58
		59
		60	58 \| DMW1 = (DMAA & WD & RW' & PHI2)
		61	59 \|\| RD, WR SINCRONIZZATI CON EN (WD = 0)
		62	60 \| DMR2 = (DMAA & WD' & RW & EN)
		63	61 \| DMW2 = (DMAA & WD' & RW' & EN)
		64	62 \| DMRD = (DMR1 # DMR2)
		65	63 \| DMWE = (DMW1 # DMW2)
		66	64 \|\|
		67	65 \|\| --------------------------------------------------------
		68	66 \|\| SEGNALI RD,WR,MRD,MWR 3 STATI PER DMA
		69	67 \|\| XAE attiva uscita 3-stati se LOW
		70	68 \| IORD = (DMRD # UMRD)
		71	69 \| IOWR = (DMWE # UMWE)
		72	70 \| MEMRD = (CX2' & RW & PHI2 & OE)
		73	71 \| MEMWRA = (CX2' & RW' & PHI2 & MW0 & OE)
		74	72 \| MEMWRB = (CX2' & RW' & PHI0 & MW0' & OE)
		75	73 \| MEMWR = (MEMWRA # MEMWRB)
		76	74 \| IOR = AEN' ?? IORD
		77	75 \| IOW = AEN' ?? IOWR
		78	76 \| MRD = AEN' ?? MEMRD
		79	77 \| MWE = AEN' ?? MEMWR
		80	78 \|\| --------------------------------------------------------
		81	79 \|\| SELEZIONE SHARED RAM
		82	80 \|\| DMA ATTIVO - RAM SEMPRE SELEZIONATA
		83	81 \| CEA = (OE')
		84	82 \|\| DMA INATTIVO
		85	83 \| CEB = (CX2' & OE & PHI2)
		86	84 \| CS3 = (CEA # CEB)
		87	85 \|\|
		88	86 \|\| --------------------------------------------------------
		89	87 \|\| ABILITAZIONE BUFFER DATI BUS DMA
		90	88 \| FDCZ1 = (FDCA & WF & PHI2)
		91	89 \| FDCZ2 = (FDCA & WF' & EN)
		92	90 \| DMAZ1 = (DMAA & WD & PHI2)
		93	91 \| DMAZ2 = (DMAA & WD' & EN)
		94	92 \| DBE = (FDCZ1 # FDCZ2 # DMAZ1 # DMAZ2 # (CX2A & PHI2))
		95
		96
		97
		98
		99
		100
		101	I202 8/11/12 5:46 pm (Saturday)
		102
		103
		104	OrCAD DEVICE FITTER v2.01 12/09/94 (Source file .\PLD\#0000.PLA)
		105
		106
		107
		108	RESOLVED EXPRESSIONS (Reduction 0)
		109
		110
		111
		112
		113
		114
		115	21 DMA WF
		116
		117	23 WD WF
		118
		119
		120	K 2 DMA FDC
		121	3 DMA WF
		122	4 FDC WD
		123	5 WD WF
		124
		125
		126	CS0 104 DMA' AEN'
		127
		128	CS1 95 FDC' AEN'
		129
		130
		131
		132
		133	75 PHI2 RW DMA' WD AEN'
		134
		135	77 RW DMA' WD' AEN' EN
		136
		137
		138	IOW 61 AEN'
		139	62 PHI2 RW' DMA' WD AEN'
		140	63 PHI2 RW' FDC' WF AEN'
		141	64 RW' DMA' WD' AEN' EN
		142
		143
		144	MRD 48 AEN'
		145	49 PHI2 RW CX2' OE
		146
		147	MWE 37 AEN'
		148
		149	39 RW' PHI0 CX2' MW0' OE
		150
		151
		152	30 OE'
		153
		154	DBE 113 PHI2 DMA' WD AEN'
		155
		156	115 DMA' WD' AEN' EN
		157	116 FDC' WF' AEN' EN
		158
		159
		160
		161
		162	SIGNAL ASSIGNMENT
		163	Rows
		164
		165
		166
		167
		168	2. RW 4 - - - High
		169	3. PHI0 8 - - - High
		170	4. CX2 12 - - - High
		171	5. DMA 16 - - - High
		172
		173	8. WD 24 - - - High
		174	9. WF 28 - - - High
		175	10. MW0 32 - - - High
		176	11. AEN 36 - - - High
		177	12. OE 40 - - - High
		178	13. EN 44 - - - High
		179	14. RDY 48 - - - High
		180	15. DBE 51 112 9 5 Low (Three-state)
		181	16. CS0 47 103 9 1 Low (Three-state)
		182	17. CS1 43 94 9 1 Low (Three-state)
		183	18. CS2 38 85 9 1 High (Three-state)
		184	19. IOR 35 74 11 5 Low (Three-state)
		185	20. IOW 31 61 13 5 Low (Three-state)
		186	22. MRD 27 48 13 2 Low (Three-state)
		187	23. MWE 23 37 11 3 Low (Three-state)
		188	24. CS3 19 28 9 2 Low (Three-state)
		189	25. J 15 19 9 5 Low (Three-state)
		190	26. PHI2N 11 10 9 1 Low (Three-state)
		191	27. K 6 1 9 5 High (Three-state)
		192	28. - 2 - - -
		193	29. - - 0 1 0
		194	30. - - 121 1 0
		195	---- ----
		196	122 36 (30%)
		197
		198
		199	I200 No fatal errors found in source code (device phase).
		200	I201 No warnings.
		201
		202
		203
		204
		205	*
		206	QP28* QF6432* QV1024*
		207
		208
		209
		210	L0156 1111111111111111011111111111011111111111111111111111*
		211	L0208 1111111111111111111101110111111111111111111111111111*
		212	L0260 1111111111111111111111110111011111111111111111111111*
		213	L0312 1111111111111111111111111111111111111111111111110111*
		214	L0520 1111111111111111111111111111111111111111111111111111*
		215	L0572 0111111111111111111111111111111111111111111111111111*
		216	L0988 1111111111111111111111111111111111111111111111111111*
		217	L1040 1111111111111111011101111111111111111111111111111111*
		218	L1092 1111111111111111011111111111011111111111111111111111*
		219	L1144 1111111111111111111101110111111111111111111111111111*
		220	L1196 1111111111111111111111110111011111111111111111111111*
		221	L1248 1111111111111111111111111111111111111111111111110111*
		222	L1456 1111111111111111111111111111111111111111111111111111*
		223	L1508 0111111111111011111111111111111111111111011111111111*
		224	L1560 1111111111111111111111111111111111111111101111111111*
		225	L1924 1111111111111111111111111111111111111011111111111111*
		226	L1976 0111101111111011111111111111111101111111011111111111*
		227	L2028 1111101101111011111111111111111110111111011111111111*
		228	L2496 1111111111111111111111111111111111111011111111111111*
		229	L2548 0111011111111011111111111111111111111111011111111111*
		230	L3172 1111111111111111111111111111111111111011111111111111*
		231	L3224 0111101111111111101111110111111111111011111111111111*
		232	L3276 0111101111111111111110111111011111111011111111111111*
		233	L3328 1111101111111111101111111011111111111011111101111111*
		234	L3380 1111101111111111111110111111101111111011111101111111*
		235	L3848 1111111111111111111111111111111111111011111111111111*
		236	L3900 0111011111111111101111110111111111111011111111111111*
		237	L3952 0111011111111111111110111111011111111011111111111111*
		238	L4004 1111011111111111101111111011111111111011111101111111*
		239	L4056 1111011111111111111110111111101111111011111101111111*
		240	L4420 1111111111111111111111111111111111111111111111111111*
		241	L4472 1111111111111111111110111111111111111011111111111111*
		242	L4888 1111111111111111111111111111111111111111111111111111*
		243	L4940 1111111111111111111110111111111111111011111111111111*
		244	L5356 1111111111111111111111111111111111111111111111111111*
		245	L5408 1111111111111111101111111111111111111011111111111111*
		246	L5824 1111111111111111111111111111111111111111111111111111*
		247	L5876 0111111111111111101111110111111111111011111111111111*
		248	L5928 0111111111111111111110111111011111111011111111111111*
		249	L5980 1111111111111111101111111011111111111011111101111111*
		250	L6032 1111111111111111111110111111101111111011111101111111*
		251	L6084 0111111111111011111111111111111111111011111111111111*
		252	L6344 1101010101010101110101010011000000110000001100000011*
		253	L6396 000000100000001000000010000000100000*
		254	C1996*
		255
		256	I202 8/11/12 5:46 pm (Saturday)
		257	I203 Memory usage 9K
		258	I204 Elapsed time 1 second
		259

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