Details | Last modification | View Log | RSS feed
| Rev | Author | Line No. | Line |
|---|---|---|---|
| 1 | - | 1 | || FILE: #0000.PLD |
| 2 | || PROJ: 20120607 |
||
| 3 | || PART: G26CV12-#0000 |
||
| 4 | || |
||
| 5 | || DEV : GAL26CV12 |
||
| 6 | || |
||
| 7 | || DESC: CONTROLLER DMA/FDC |
||
| 8 | || |
||
| 9 | | |
||
| 10 | |GAL26CV12 |
||
| 11 | | |
||
| 12 | || INPUT |
||
| 13 | | 1:PHI2, 2:RW, 3:PHI0, 4:CX2, 5:DMA, 6:FDC, 8:WD, 9:WF, 10:MW0, |
||
| 14 | | 11:AEN, 12:OE, 13:EN, 14:RDY, 28:-, |
||
| 15 | || OUTPUT |
||
| 16 | | 15:DBE, 16:CS0, 17:CS1, 18:CS2, 19:IOR, 20:IOW, 22:MRD, 23:MWE, |
||
| 17 | | 24:CS3, 25:J, 26:PHI2N, 27:K |
||
| 18 | | |
||
| 19 | | ACTIVE-LOW: DBE, CS0, CS1, IOR, IOW, MRD, MWE, CS3, J, PHI2N |
||
| 20 | | |
||
| 21 | | |
||
| 22 | | SIGNATURE: "0000 " |
||
| 23 | | |
||
| 24 | || -------------------------------------------------------- |
||
| 25 | || SEGNALI COMANDO FLIP-FLOP WAIT |
||
| 26 | | PHI2N = PHI2 |
||
| 27 | || ABILITAZIONE WAIT |
||
| 28 | | WTX = ((DMA' & WD') # (FDC' & WF')) |
||
| 29 | || COMANDO J,K |
||
| 30 | | DATA = (RDY # WTX') |
||
| 31 | | J = DATA |
||
| 32 | | K = DATA |
||
| 33 | || |
||
| 34 | || -------------------------------------------------------- |
||
| 35 | || CHIP SELECT RAM, DMA & FDC VALIDI SOLO SE AEN = 0 |
||
| 36 | | DMAA = (DMA' & AEN') |
||
| 37 | | FDCA = (FDC' & AEN') |
||
| 38 | | CX2A = (CX2' & AEN') |
||
| 39 | | CS0 = DMAA |
||
| 40 | | CS1 = FDCA |
||
| 41 | | CS2 = FDCA |
||
| 42 | || |
||
| 43 | || -------------------------------------------------------- |
||
| 44 | || SEGNALI UM8388 RD, WR (FDC) |
||
| 45 | || RD, WR SINCRONIZZATI CON PHI2 (WF = 1) |
||
| 46 | | UMR1 = (FDCA & WF & RW & PHI2) |
||
| 47 | | UMW1 = (FDCA & WF & RW' & PHI2) |
||
| 48 | || RD, WR SINCRONIZZATI CON EN (WF = 0) |
||
| 49 | | UMR2 = (FDCA & WF' & RW & EN) |
||
| 50 | | UMW2 = (FDCA & WF' & RW' & EN) |
||
| 51 | | UMRD = (UMR1 # UMR2) |
||
| 52 | | UMWE = (UMW1 # UMW2) |
||
| 53 | || |
||
| 54 | || -------------------------------------------------------- |
||
| 55 | || SEGNALI 82C37 RD, WR (DMA) |
||
| 56 | || RD, WR SINCRONIZZATI CON PHI2 (WD = 1) |
||
| 57 | | DMR1 = (DMAA & WD & RW & PHI2) |
||
| 58 | | DMW1 = (DMAA & WD & RW' & PHI2) |
||
| 59 | || RD, WR SINCRONIZZATI CON EN (WD = 0) |
||
| 60 | | DMR2 = (DMAA & WD' & RW & EN) |
||
| 61 | | DMW2 = (DMAA & WD' & RW' & EN) |
||
| 62 | | DMRD = (DMR1 # DMR2) |
||
| 63 | | DMWE = (DMW1 # DMW2) |
||
| 64 | || |
||
| 65 | || -------------------------------------------------------- |
||
| 66 | || SEGNALI RD,WR,MRD,MWR 3 STATI PER DMA |
||
| 67 | || XAE attiva uscita 3-stati se LOW |
||
| 68 | | IORD = (DMRD # UMRD) |
||
| 69 | | IOWR = (DMWE # UMWE) |
||
| 70 | | MEMRD = (CX2' & RW & PHI2 & OE) |
||
| 71 | | MEMWRA = (CX2' & RW' & PHI2 & MW0 & OE) |
||
| 72 | | MEMWRB = (CX2' & RW' & PHI0 & MW0' & OE) |
||
| 73 | | MEMWR = (MEMWRA # MEMWRB) |
||
| 74 | | IOR = AEN' ?? IORD |
||
| 75 | | IOW = AEN' ?? IOWR |
||
| 76 | | MRD = AEN' ?? MEMRD |
||
| 77 | | MWE = AEN' ?? MEMWR |
||
| 78 | || -------------------------------------------------------- |
||
| 79 | || SELEZIONE SHARED RAM |
||
| 80 | || DMA ATTIVO - RAM SEMPRE SELEZIONATA |
||
| 81 | | CEA = (OE') |
||
| 82 | || DMA INATTIVO |
||
| 83 | | CEB = (CX2' & OE & PHI2) |
||
| 84 | | CS3 = (CEA # CEB) |
||
| 85 | || |
||
| 86 | || -------------------------------------------------------- |
||
| 87 | || ABILITAZIONE BUFFER DATI BUS DMA |
||
| 88 | | DBE = (FDCA # DMAA # CX2A) |