WebSVN – MB01 Project – Blame – /trunk/gal/20120604-MB01-RM4/PLD/#0056.LST

Rev	Author	Line No.	Line
1	-	1	OrCAD LOGIC COMPILER v2.01 N 12/09/94 (Source file .\PLD\#0056.PLD)
		2
		3	1 \|\| FILE: #0056.PLD
		4	2 \|\| PROJ: 20120401
		5	3 \|\| PART: G26CV12-#0056
		6	4 \|\|
		7	5 \|\| DEV : GAL26CV12
		8	6 \|\|
		9	7 \|\| DESC: DECODER SCHEDE RAM 4Mb
		10	8 \|\|
		11	9 \|
		12	10 \|GAL26CV12
		13	11 \|
		14	12 \|\| INPUT
		15	13 \| 1:A19, 2:A20, 3:A21, 4:A22, 5:A23, 6:PHI0, 8:RW, 9:ME, 10:PHI2,
		16	14 \| 11:FE, 12:S0, 13:S1, 14:MW0, 28:LST,
		17	15 \|\| OUTPUT
		18	16 \| 15:CS0, 16:CS1, 17:CS2, 18:CS3, 19:RD, 20:WR, 22:G,
		19	17 \| 23:CS4, 24:CS5, 25:CS6, 26:CS7, 27:CSF
		20	18 \|
		21	19 \| ACTIVE-LOW: CS0, CS1, CS2, CS3, CS4, CS5, CS6, CS7, RD, WR, G, CSF
		22	20 \|
		23	21 \|
		24	22 \| SIGNATURE: "0056 "
		25	23 \|
		26	24 \|\|
		27	25 \|\| --------------------------------------------------------
		28	26 \|\| S0, S1 -> SELEZIONE BLOCCO
		29	27 \|\| /MW0 -> QUALIFICA WRITE CON PHI0
		30	28 \|\| /FE -> ABILITA FLASH F00000 - F7FFFF (512K)
		31	29 \|\| /ME -> ABILITA RAM
		32	30 \|\| LST -> ABILITA SLOT (CSF) PER FLASH
		33	31 \|\| --------------------------------------------------------
		34	32 \|\|
		35	33 \|\| BLOCCHI SELEZIONE RAM 4MB
		36	34 \|\| BLK0 -> 000000 - 3FFFFF (S0 = 0, S1 = 0)
		37	35 \| BLK0 = (A23' & A22' & S1' & S0' & ME' & FE)
		38	36 \|\| BLK1 -> 400000 - 7FFFFF (S0 = 1, S1 = 0)
		39	37 \| BLK1 = (A23' & A22 & S1' & S0 & ME' & FE)
		40	38 \|\| BLK2 -> 800000 - BFFFFF (S0 = 0, S1 = 1)
		41	39 \| BLK2 = (A23 & A22' & S1 & S0' & ME' & FE)
		42	40 \|\| BLK3 -> C00000 - FFFFFF (S0 = 1, S1 = 1)
		43	41 \| BLK3 = (A23 & A22 & S1 & S0 & ME' & FE)
		44	42 \|\| BK3F -> C00000 - FFFFFF (S0 = 1, S1 = 1) FLASH (FE=0, LST=1)
		45	43 \| BK3F = (A23 & A22 & S1 & S0 & ME & FE' & LST)
		46	44 \| SLF = (BK3F & A21 & A20 & A19')
		47	45 \|\| --------------------------------------------------------
		48	46 \|\|
		49	47 \|\| SELEZIONE RAM
		50	48 \| SLM = (BLK0 # BLK1 # BLK2 # BLK3)
		51	49 \| SEL = (SLF # SLM)
		52	50 \| CS0 = (SLM & A21' & A20' & A19' & PHI2)
		53	51 \| CS1 = (SLM & A21' & A20' & A19 & PHI2)
		54	52 \| CS2 = (SLM & A21' & A20 & A19' & PHI2)
		55	53 \| CS3 = (SLM & A21' & A20 & A19 & PHI2)
		56	54 \| CS4 = (SLM & A21 & A20' & A19' & PHI2)
		57	55 \| CS5 = (SLM & A21 & A20' & A19 & PHI2)
		58
		59
		60	58 \| G = SEL
		61	59 \| CSF = (SLF & PHI2)
		62	60 \| RD = (SEL & PHI2 & RW)
		63	61 \| WRA = (SEL & PHI2 & RW' & MW0)
		64	62 \| WRB = (SEL & PHI0 & RW' & MW0')
		65	63 \| WR = (WRA # WRB)
		66
		67
		68
		69
		70
		71
		72	I202 8/13/12 12:23 pm (Monday)
		73
		74
		75	OrCAD DEVICE FITTER v2.01 12/09/94 (Source file .\PLD\#0056.PLA)
		76
		77
		78
		79	RESOLVED EXPRESSIONS (Reduction 0)
		80
		81
		82
		83
		84	114 A19' A20' A21' A22' A23 ME' PHI2 FE S0' S1
		85
		86	116 A19' A20' A21' A22 A23 ME' PHI2 FE S0 S1
		87
		88	CS1 104 A19 A20' A21' A22' A23' ME' PHI2 FE S0' S1'
		89	105 A19 A20' A21' A22' A23 ME' PHI2 FE S0' S1
		90	106 A19 A20' A21' A22 A23' ME' PHI2 FE S0 S1'
		91	107 A19 A20' A21' A22 A23 ME' PHI2 FE S0 S1
		92
		93	CS2 95 A19' A20 A21' A22' A23' ME' PHI2 FE S0' S1'
		94	96 A19' A20 A21' A22' A23 ME' PHI2 FE S0' S1
		95	97 A19' A20 A21' A22 A23' ME' PHI2 FE S0 S1'
		96	98 A19' A20 A21' A22 A23 ME' PHI2 FE S0 S1
		97
		98	CS3 86 A19 A20 A21' A22' A23' ME' PHI2 FE S0' S1'
		99	87 A19 A20 A21' A22' A23 ME' PHI2 FE S0' S1
		100	88 A19 A20 A21' A22 A23' ME' PHI2 FE S0 S1'
		101	89 A19 A20 A21' A22 A23 ME' PHI2 FE S0 S1
		102
		103	CS4 38 A19' A20' A21 A22' A23' ME' PHI2 FE S0' S1'
		104	39 A19' A20' A21 A22' A23 ME' PHI2 FE S0' S1
		105	40 A19' A20' A21 A22 A23' ME' PHI2 FE S0 S1'
		106	41 A19' A20' A21 A22 A23 ME' PHI2 FE S0 S1
		107
		108	CS5 29 A19 A20' A21 A22' A23' ME' PHI2 FE S0' S1'
		109	30 A19 A20' A21 A22' A23 ME' PHI2 FE S0' S1
		110	31 A19 A20' A21 A22 A23' ME' PHI2 FE S0 S1'
		111	32 A19 A20' A21 A22 A23 ME' PHI2 FE S0 S1
		112
		113	CS6 20 A19' A20 A21 A22' A23' ME' PHI2 FE S0' S1'
		114	21 A19' A20 A21 A22' A23 ME' PHI2 FE S0' S1
		115	22 A19' A20 A21 A22 A23' ME' PHI2 FE S0 S1'
		116	23 A19' A20 A21 A22 A23 ME' PHI2 FE S0 S1
		117
		118	CS7 11 A19 A20 A21 A22' A23' ME' PHI2 FE S0' S1'
		119	12 A19 A20 A21 A22' A23 ME' PHI2 FE S0' S1
		120	13 A19 A20 A21 A22 A23' ME' PHI2 FE S0 S1'
		121	14 A19 A20 A21 A22 A23 ME' PHI2 FE S0 S1
		122
		123	G 49 A19' A20 A21 A22 A23 ME FE' S0 S1 LST
		124	50 A22' A23' ME' FE S0' S1'
		125	51 A22' A23 ME' FE S0' S1
		126	52 A22 A23' ME' FE S0 S1'
		127
		128
		129	CSF 2 A19' A20 A21 A22 A23 ME PHI2 FE' S0 S1 LST
		130
		131	RD 75 A19' A20 A21 A22 A23 RW ME PHI2 FE' S0 S1 LST
		132	76 A22' A23' RW ME' PHI2 FE S0' S1'
		133
		134	78 A22 A23' RW ME' PHI2 FE S0 S1'
		135
		136
		137	WR 62 A19' A20 A21 A22 A23 PHI0 RW' ME FE' S0 S1 MW0'
		138	LST
		139	63 A19' A20 A21 A22 A23 RW' ME PHI2 FE' S0 S1 MW0
		140	LST
		141
		142
		143	66 A22' A23 PHI0 RW' ME' FE S0' S1 MW0'
		144	67 A22' A23 RW' ME' PHI2 FE S0' S1 MW0
		145	68 A22 A23' PHI0 RW' ME' FE S0 S1' MW0'
		146	69 A22 A23' RW' ME' PHI2 FE S0 S1' MW0
		147	70 A22 A23 PHI0 RW' ME' FE S0 S1 MW0'
		148	71 A22 A23 RW' ME' PHI2 FE S0 S1 MW0
		149
		150
		151
		152	SIGNAL ASSIGNMENT
		153	Rows
		154	Pin Signal name Column -------------- Activity
		155
		156
		157
		158
		159	3. A21 8 - - - High
		160	4. A22 12 - - - High
		161	5. A23 16 - - - High
		162	6. PHI0 20 - - - High
		163
		164	9. ME 28 - - - High
		165	10. PHI2 32 - - - High
		166	11. FE 36 - - - High
		167	12. S0 40 - - - High
		168	13. S1 44 - - - High
		169	14. MW0 48 - - - High
		170	15. CS0 51 112 9 4 Low (Three-state)
		171	16. CS1 47 103 9 4 Low (Three-state)
		172	17. CS2 43 94 9 4 Low (Three-state)
		173	18. CS3 39 85 9 4 Low (Three-state)
		174	19. RD 35 74 11 5 Low (Three-state)
		175	20. WR 31 61 13 10 Low (Three-state)
		176	22. G 27 48 13 5 Low (Three-state)
		177	23. CS4 23 37 11 4 Low (Three-state)
		178	24. CS5 19 28 9 4 Low (Three-state)
		179	25. CS6 15 19 9 4 Low (Three-state)
		180	26. CS7 11 10 9 4 Low (Three-state)
		181	27. CSF 7 1 9 1 Low (Three-state)
		182	28. LST 2 - - - High
		183	29. - - 0 1 0
		184	30. - - 121 1 0
		185	---- ----
		186	122 53 (43%)
		187
		188
		189	I200 No fatal errors found in source code (device phase).
		190	I201 No warnings.
		191
		192
		193	OrCAD DEVICE
		194
		195
		196	QP28* QF6432* QV1024*
		197	F0*
		198
		199
		200
		201	L0572 0111011101111011101111111111101101110111101110111111*
		202	L0624 0111011101111011011111111111101101110111101101111111*
		203	L0676 0111011101110111101111111111101101110111011110111111*
		204	L0728 0111011101110111011111111111101101110111011101111111*
		205	L0988 1111111111111111111111111111111111111111111111111111*
		206	L1040 1011011101111011101111111111101101110111101110111111*
		207	L1092 1011011101111011011111111111101101110111101101111111*
		208	L1144 1011011101110111101111111111101101110111011110111111*
		209	L1196 1011011101110111011111111111101101110111011101111111*
		210	L1456 1111111111111111111111111111111111111111111111111111*
		211	L1508 0111101101111011101111111111101101110111101110111111*
		212	L1560 0111101101111011011111111111101101110111101101111111*
		213	L1612 0111101101110111101111111111101101110111011110111111*
		214	L1664 0111101101110111011111111111101101110111011101111111*
		215	L1924 1111111111111111111111111111111111111111111111111111*
		216	L1976 1011101101111011101111111111101101110111101110111111*
		217	L2028 1011101101111011011111111111101101110111101101111111*
		218	L2080 1011101101110111101111111111101101110111011110111111*
		219	L2132 1011101101110111011111111111101101110111011101111111*
		220	L2496 1111111111111111111111111111111111111111111111111111*
		221	L2548 1001011101110111011111111111011111111011011101111111*
		222	L2600 1111111111111011101111111111101111110111101110111111*
		223	L2652 1111111111111011011111111111101111110111101101111111*
		224	L2704 1111111111110111101111111111101111110111011110111111*
		225	L2756 1111111111110111011111111111101111110111011101111111*
		226	L3172 1111111111111111111111111111111111111111111111111111*
		227	L3224 1001011101110111011101111011011111111011011101111011*
		228	L3276 1001011101110111011111111011011101111011011101110111*
		229	L3328 1111111111111011101101111011101111110111101110111011*
		230	L3380 1111111111111011101111111011101101110111101110110111*
		231	L3432 1111111111111011011101111011101111110111101101111011*
		232	L3484 1111111111111011011111111011101101110111101101110111*
		233	L3536 1111111111110111101101111011101111110111011110111011*
		234	L3588 1111111111110111101111111011101101110111011110110111*
		235	L3640 1111111111110111011101111011101111110111011101111011*
		236	L3692 1111111111110111011111111011101101110111011101110111*
		237	L3848 1111111111111111111111111111111111111111111111111111*
		238	L3900 1001011101110111011111110111011101111011011101111111*
		239	L3952 1111111111111011101111110111101101110111101110111111*
		240	L4004 1111111111111011011111110111101101110111101101111111*
		241	L4056 1111111111110111101111110111101101110111011110111111*
		242	L4108 1111111111110111011111110111101101110111011101111111*
		243	L4420 1111111111111111111111111111111111111111111111111111*
		244	L4472 0111011110111011101111111111101101110111101110111111*
		245	L4524 0111011110111011011111111111101101110111101101111111*
		246	L4576 0111011110110111101111111111101101110111011110111111*
		247	L4628 0111011110110111011111111111101101110111011101111111*
		248	L4888 1111111111111111111111111111111111111111111111111111*
		249	L4940 1011011110111011101111111111101101110111101110111111*
		250	L4992 1011011110111011011111111111101101110111101101111111*
		251	L5044 1011011110110111101111111111101101110111011110111111*
		252	L5096 1011011110110111011111111111101101110111011101111111*
		253	L5356 1111111111111111111111111111111111111111111111111111*
		254	L5408 0111101110111011101111111111101101110111101110111111*
		255	L5460 0111101110111011011111111111101101110111101101111111*
		256	L5512 0111101110110111101111111111101101110111011110111111*
		257	L5564 0111101110110111011111111111101101110111011101111111*
		258
		259	L5876 1011101110111011101111111111101101110111101110111111*
		260	L5928 1011101110111011011111111111101101110111101101111111*
		261	L5980 1011101110110111101111111111101101110111011110111111*
		262	L6032 1011101110110111011111111111101101110111011101111111*
		263	L6344 0101010101010101010101010011000000110000001101010011*
		264	L6396 011000100000001000000010000000100000*
		265	C8FBB*
		266
		267	I202 8/13/12 12:23 pm (Monday)
		268	I203 Memory usage 16K
		269	I204 Elapsed time 1 second
		270

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