Details | Last modification | View Log | RSS feed
| Rev | Author | Line No. | Line |
|---|---|---|---|
| 1 | - | 1 | || FILE: #0160.PLD |
| 2 | || PROJ: 20120600 |
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| 3 | || PART: G16V8-#0160 |
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| 4 | || |
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| 5 | || DEV : GAL16V8 |
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| 6 | || |
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| 7 | || DESC: VDC CONTROL |
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| 8 | || |
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| 9 | | |
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| 10 | |GAL16V8A |
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| 11 | | |
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| 12 | || INPUT |
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| 13 | | 1:VDC, 2:PHI2, 3:RW, 4:PHI0, 5:-, 6:WV, 7:EN2, 8:S0, 9:F16, 11:S16, |
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| 14 | | 12:F20, 13:S1, 14:SX, |
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| 15 | || OUTPUT |
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| 16 | | 15:CS0, 16:CS1, 17:DCLK, 18:M16, 19:M20 |
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| 17 | | |
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| 18 | | ACTIVE-LOW: CS0 |
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| 19 | | |
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| 20 | | PROPERTY:"SIMPLE" |
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| 21 | | |
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| 22 | | SIGNATURE: "0160 " |
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| 23 | | |
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| 24 | || -------------------------------------------------------- |
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| 25 | || SELEZIONE DCLK PER MOS8563 (S16=0 ->16MHz, S16=1->20MHz) |
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| 26 | | DCLK = ((S16 & F20) # (S16' & F16)) |
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| 27 | | M16 = F16 |
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| 28 | | M20 = F20 |
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| 29 | || -------------------------------------------------------- |
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| 30 | || ABILITAZIONE MOS8563 |
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| 31 | | VDCA = VDC' |
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| 32 | || -------------------------------------------------------- |
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| 33 | || ABILITAZIONE MOS8563 (VDC, WAIT -> WV) |
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| 34 | || CICLO READ |
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| 35 | || VR1 = (VDCA & WV & RW & PHI2) |
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| 36 | || VR2 = (VDCA & WV' & RW & EN2) |
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| 37 | || VR1 = (VDCA & WV & RW) |
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| 38 | || VR2 = (VDCA & WV' & RW) |
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| 39 | | VR1 = (VDCA & WV & RW & PHI2 & S0) |
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| 40 | | VR2 = (VDCA & WV' & RW & EN2) |
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| 41 | | VR3 = (VDCA & WV & RW & PHI0 & S0') |
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| 42 | |||
| 43 | || CICLO WRITE SINCRONIZZATO CON PHI2 (S0 = 1) |
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| 44 | | VW1 = (VDCA & WV & RW' & PHI2 & S0) |
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| 45 | | VW2 = (VDCA & WV' & RW' & EN2 & S0) |
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| 46 | || CICLO WRITE SINCRONIZZATO CON PHI0 (S0 = 0) |
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| 47 | || VW3 = (VDCA & WV & RW' & PHI0 & S0') |
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| 48 | || VW4 = (VDCA & WV' & RW' & EN0 & S0') |
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| 49 | | VW3 = (VDCA & WV & RW' & PHI0 & S0') |
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| 50 | | VW4 = (VDCA & WV' & RW' & EN2 & S0') |
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| 51 | || |
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| 52 | || ABILITAZIONE VDC |
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| 53 | | VDCB = (VR1 # VR2 # VR3 # VW1 # VW2 # VW3 # VW4) |
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| 54 | || S1 = 1 -> /CS0 QUALIFICATO CON PHI2,EN |
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| 55 | || CS1 = 1 SE SX = 1 |
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| 56 | || CS1 = VDCA SE SX = 0 |
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| 57 | | CS0A = (VDCB & S1) |
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| 58 | | CS1A = (VDCA & S1 & SX') |
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| 59 | | CS1X = (S1 & SX) |
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| 60 | || S1 = 0 -> CS1 QUALIFICATO CON PHI2,EN |
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| 61 | || /CS0 = 0 SE SX = 1 |
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| 62 | || /CS0 = /VDC SE SX = 0 |
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| 63 | | CS1B = (VDCB & S1') |
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| 64 | | CS0B = (VDCA & S1' & SX') |
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| 65 | | CS0X = (S1' & SX) |
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| 66 | | CS0 = (CS0A # CS0B # CS0X) |
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| 67 | | CS1 = (CS1A # CS1B # CS1X) |