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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 1 | - | 1 | OrCAD LOGIC COMPILER v2.01 N 12/09/94 (Source file .\PLD\#0160.PLD) |
| 2 | |||
| 3 | 1 || FILE: #0160.PLD |
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| 4 | 2 || PROJ: 20120600 |
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| 5 | 3 || PART: G16V8-#0160 |
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| 6 | 4 || |
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| 7 | 5 || DEV : GAL16V8 |
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| 8 | 6 || |
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| 9 | 7 || DESC: VDC CONTROL |
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| 10 | 8 || |
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| 11 | 9 | |
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| 12 | 10 |GAL16V8A |
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| 13 | 11 | |
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| 14 | 12 || INPUT |
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| 15 | 13 | 1:VDC, 2:PHI2, 3:RW, 4:PHI0, 5:-, 6:WV, 7:EN2, 8:S0, 9:F16, 11:S16, |
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| 16 | 14 | 12:F20, 13:S1, 14:SX, |
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| 17 | 15 || OUTPUT |
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| 18 | 16 | 15:CS0, 16:CS1, 17:DCLK, 18:M16, 19:M20 |
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| 19 | 17 | |
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| 20 | 18 | ACTIVE-LOW: CS0 |
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| 21 | 19 | |
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| 22 | 20 | PROPERTY:"SIMPLE" |
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| 23 | 21 | |
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| 24 | 22 | SIGNATURE: "0160 " |
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| 25 | 23 | |
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| 26 | 24 || -------------------------------------------------------- |
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| 27 | 25 || SELEZIONE DCLK PER MOS8563 (S16=0 ->16MHz, S16=1->20MHz) |
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| 28 | 26 | DCLK = ((S16 & F20) # (S16' & F16)) |
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| 29 | 27 | M16 = ((F20 & S1) # (F16 & S1')) |
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| 30 | 28 | M20 = ((F16 & S1) # (F20 & S1')) |
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| 31 | 29 || -------------------------------------------------------- |
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| 32 | 30 || ABILITAZIONE MOS8563 |
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| 33 | 31 | VDCA = VDC' |
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| 34 | 32 || -------------------------------------------------------- |
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| 35 | 33 || ABILITAZIONE MOS8563 (VDC, WAIT -> WV) |
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| 36 | 34 || CICLO READ |
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| 37 | 35 || VR1 = (VDCA & WV & RW & PHI2) |
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| 38 | 36 || VR2 = (VDCA & WV' & RW & EN2) |
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| 39 | 37 || VR1 = (VDCA & WV & RW) |
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| 40 | 38 || VR2 = (VDCA & WV' & RW) |
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| 41 | 39 || VR1 = (VDCA & WV & RW & PHI2 & S1) |
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| 42 | 40 | VR1 = (VDCA & WV & RW & PHI2) |
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| 43 | 41 | VR2 = (VDCA & WV' & RW & EN2) |
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| 44 | 42 || VR3 = (VDCA & WV & RW & PHI0 & S1') |
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| 45 | 43 |
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| 46 | 44 || CICLO WRITE SINCRONIZZATO CON PHI2 (S0 = 1) |
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| 47 | 45 | VW1 = (VDCA & WV & RW' & PHI2 & S0) |
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| 48 | 46 | VW2 = (VDCA & WV' & RW' & EN2) |
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| 49 | 47 || CICLO WRITE SINCRONIZZATO CON PHI0 (S0 = 0) |
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| 50 | 48 || VW3 = (VDCA & WV & RW' & PHI0 & S0') |
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| 51 | 49 || VW4 = (VDCA & WV' & RW' & EN0 & S0') |
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| 52 | 50 | VW3 = (VDCA & WV & RW' & PHI0 & S0') |
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| 53 | 51 || VW4 = (VDCA & WV' & RW' & EN2 & S0') |
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| 54 | 52 || |
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| 55 | 53 || ABILITAZIONE VDC |
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| 56 | 54 || VDCB = (VR1 # VR2 # VR3 # VW1 # VW2 # VW3) |
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| 57 | 55 | VDCB = (VR1 # VR2 # VW1 # VW2 # VW3) |
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| 58 | |||
| 59 | |||
| 60 | 58 || CS1 = VDCA SE SX = 0 |
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| 61 | 59 | CS1A = (VDCA & SX') |
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| 62 | 60 | CS1X = (SX) |
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| 63 | 61 | CS0 = (VDCB) |
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| 64 | 62 | CS1 = (CS1A # CS1X) |
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| 65 | |||
| 66 | |||
| 67 | |||
| 68 | |||
| 69 | |||
| 70 | |||
| 71 | I202 9/6/12 11:18 am (Thursday) |
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| 72 | |||
| 73 | |||
| 74 | OrCAD DEVICE FITTER v2.01 12/09/94 (Source file .\PLD\#0160.PLA) |
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| 75 | |||
| 76 | I289 Simple GAL architecture selected. |
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| 77 | |||
| 78 | |||
| 79 | |||
| 80 | |||
| 81 | |||
| 82 | |||
| 83 | |||
| 84 | 17 S16 F20 |
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| 85 | |||
| 86 | M16 8 F16 S1' |
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| 87 | |||
| 88 | |||
| 89 | M20 0 F16 S1 |
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| 90 | |||
| 91 | |||
| 92 | CS0 32 VDC' PHI2 RW' WV S0 |
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| 93 | |||
| 94 | 34 VDC' PHI2 RW WV |
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| 95 | 35 VDC' RW' WV' EN2 |
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| 96 | |||
| 97 | |||
| 98 | CS1 24 VDC' SX' |
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| 99 | 25 SX |
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| 100 | |||
| 101 | |||
| 102 | |||
| 103 | SIGNAL ASSIGNMENT |
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| 104 | Rows |
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| 105 | |||
| 106 | |||
| 107 | |||
| 108 | |||
| 109 | 2. PHI2 0 - - - High |
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| 110 | 3. RW 4 - - - High |
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| 111 | 4. PHI0 8 - - - High |
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| 112 | 5. - 12 - - - |
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| 113 | |||
| 114 | 7. EN2 20 - - - High |
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| 115 | 8. S0 24 - - - High |
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| 116 | 9. F16 28 - - - High |
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| 117 | 11. S16 30 - - - High (Enable) |
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| 118 | 12. F20 26 56 8 0 High |
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| 119 | 13. S1 22 48 8 0 High |
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| 120 | 14. SX 18 40 8 0 High |
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| 121 | 15. CS0 1 32 8 5 Low |
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| 122 | 16. CS1 0 24 8 2 High |
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| 123 | 17. DCLK 14 16 8 2 High |
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| 124 | 18. M16 10 8 8 2 High |
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| 125 | 19. M20 6 0 8 2 High |
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| 126 | ---- ---- |
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| 127 | 64 13 (20%) |
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| 128 | |||
| 129 | |||
| 130 | I200 No fatal errors found in source code (device phase). |
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| 131 | I201 No warnings. |
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| 132 | |||
| 133 | |||
| 134 | |||
| 135 | |||
| 136 | * |
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| 137 | QP20* QF2194* QV1024* |
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| 138 | |||
| 139 | |||
| 140 | |||
| 141 | L0256 11 11 11 11 11 11 11 11 11 11 11 10 11 11 01 11 * |
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| 142 | L0288 11 11 11 11 11 11 11 11 11 11 11 01 11 01 11 11 * |
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| 143 | L0512 11 11 11 11 11 11 11 11 11 11 11 11 11 11 01 10 * |
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| 144 | L0544 11 11 11 11 11 11 11 11 11 11 11 11 11 01 11 01 * |
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| 145 | L0768 11 10 11 11 11 11 11 11 11 10 11 11 11 11 11 11 * |
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| 146 | L0800 11 11 11 11 11 11 11 11 11 01 11 11 11 11 11 11 * |
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| 147 | L1024 01 10 10 11 11 11 11 11 01 11 11 11 01 11 11 11 * |
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| 148 | L1056 11 10 10 11 01 11 11 11 01 11 11 11 10 11 11 11 * |
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| 149 | L1088 01 10 01 11 11 11 11 11 01 11 11 11 11 11 11 11 * |
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| 150 | L1120 11 10 10 11 11 11 11 11 10 11 01 11 11 11 11 11 * |
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| 151 | L1152 11 10 01 11 11 11 11 11 10 11 01 11 11 11 11 11 * |
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| 152 | L2048 11 11 01 11 00 11 00 00 00 11 00 01 00 11 01 10 * |
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| 153 | L2080 00 11 00 00 00 10 00 00 00 10 00 00 00 10 00 00 * |
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| 154 | L2112 00 10 00 00 00 00 01 11 11 11 11 11 11 11 11 11 * |
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| 155 | L2144 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 * |
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| 156 | L2176 11 11 11 11 11 11 11 11 10 * |
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| 157 | C3B4F* |
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| 158 | |||
| 159 | I202 9/6/12 11:18 am (Thursday) |
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| 160 | I203 Memory usage 6K |
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| 161 | I204 Elapsed time 1 second |
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| 162 |