WebSVN – MB01 Project – Blame – /trunk/gal/20120600-MB01-MOTHERBOARD/PLD/#0151B.LST

Rev	Author	Line No.	Line
1	-	1	OrCAD LOGIC COMPILER v2.01 N 12/09/94 (Source file .\PLD\#0151B.PLD)
		2
		3	1 \|\| FILE: #0151.PLD
		4	2 \|\| PROJ: 20120600
		5	3 \|\| PART: G20V8-#0151
		6	4 \|\|
		7	5 \|\| DEV : GAL20V8
		8	6 \|\|
		9	7 \|\| DESC: DECODER I/O WAIT
		10	8 \|\|
		11	9 \|
		12	10 \|GAL20V8A
		13	11 \|
		14	12 \|\| INPUT
		15	13 \| 1:A0, 2:A1, 3:A2, 4:A3, 5:A4, 6:A5, 7:A6, 8:A7,
		16	14 \| 9:IO1, 10:-, 11:WA0, 13:WA1, 14:WV, 23:WT,
		17	15 \|\| OUTPUT
		18	16 \| 15:ATA0, 16:ATA1, 17:DMA, 18:FDC, 19:VDC, 20:IOX, 21:PIA, 22:WAIT
		19	17 \|
		20	18 \| ACTIVE-LOW: ATA0, ATA1, DMA, FDC, VDC, IOX, PIA, WAIT
		21	19 \|
		22	20 \| PROPERTY: "SIMPLE"
		23	21 \|
		24	22 \| SIGNATURE: "0151B "
		25	23 \|
		26	24 \|\| --------------------------------------------------------
		27	25 \|\| ATA 0/1
		28	26 \|\| ATA0A => FE20 - FE27 (ATA 0)
		29	27 \| ATA0A = (IO1' & A7' & A6' & A5 & A4' & A3')
		30	28 \|\| ATA0B => FE2E - FF2F (ATA 0)
		31	29 \| ATA0B = (IO1' & A7' & A6' & A5 & A4' & A3 & A2 & A1)
		32	30 \|\| ATA0C => FE2C (ATA 0)
		33	31 \| ATA0C = (IO1' & A7' & A6' & A5 & A4' & A3 & A2 & A1' & A0')
		34	32 \|\| ATA1A => FE30 - FE37 (ATA 1)
		35	33 \| ATA1A = (IO1' & A7' & A6' & A5 & A4 & A3')
		36	34 \|\| ATA1B => FE3E - FE3F (ATA 1)
		37	35 \| ATA1B = (IO1' & A7' & A6' & A5 & A4 & A3 & A2 & A1)
		38	36 \|\| ATA1C => FE3C (ATA 1)
		39	37 \| ATA1C = (IO1' & A7' & A6' & A5 & A4 & A3 & A2 & A1' & A0')
		40	38 \|\|
		41	39 \|\| SELEZIONE ATA 0 -> FE20 - FE27, FE2C, FE2E - FE2F
		42	40 \| ATA0 = (ATA0A # ATA0B # ATA0C)
		43	41 \|\| SELEZIONE ATA 1 -> FE30 - FE37, FE3C, FE3E - FE3F
		44	42 \| ATA1 = (ATA1A # ATA1B # ATA1C)
		45	43 \|\|
		46	44 \|\| --------------------------------------------------------
		47	45 \|\| DMA & FDC
		48	46 \|\| DMA -> FE60 - FE6F
		49	47 \| DMAS = (IO1' & A7' & A6 & A5 & A4')
		50	48 \|\| FDC -> FE58 - FE5F
		51	49 \| FDCS = (IO1' & A7' & A6 & A5' & A4 & A3 & WA0 & WA1)
		52	50 \| DMA = DMAS & WA0 & WA1
		53	51 \|\|
		54	52 \|\| NEW FDC/DMA/ATA BOARD - FD80..FDDF
		55	53 \| NEWA = (IO1' & A7 & A6' & WA0' & WA1')
		56	54 \| NEWB = (IO1' & A7 & A6 & A5' & WA0' & WA1')
		57	55 \| FDC = (FDCS # NEWA # NEWB)
		58
		59
		60	58 \|\| IOY -> FE40 - FE4F
		61	59 \| IOY = (IO1' & A7' & A6 & A5' & A4')
		62	60 \|\| RTC -> FE4C - FE4D
		63	61 \| RTCA = (IOY & A3 & A2 & A1')
		64	62 \|\| VDC -> FE4E - FE4F
		65	63 \| VDCA = (IOY & A3 & A2 & A1)
		66	64 \|\| CTC -> FE48 - FE4B
		67	65 \| CTCA = (IOY & A3 & A2')
		68	66 \|\| SELEZIONE RTC, CTC
		69	67 \| IOX = (RTCA # CTCA)
		70	68 \| VDC = VDCA
		71	69 \|\| WAIT CTC
		72	70 \| WCTC = (CTCA & WT')
		73	71 \|\| WAIT VDC
		74	72 \| WVDC = (VDCA & WV')
		75	73 \|\|
		76	74 \|\| --------------------------------------------------------
		77	75 \|\| PIA -> FE28 - FE2B
		78	76 \| PIA = (IO1' & A7' & A6' & A5 & A4' & A3 & A2')
		79	77 \|\|
		80	78 \|\| --------------------------------------------------------
		81	79 \|\| SEGNALE WAIT
		82	80 \| WAIT = (WCTC # WVDC)
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		89	I202 7/22/17 5:40 pm (Saturday)
		90
		91
		92	OrCAD DEVICE FITTER v2.01 12/09/94 (Source file .\PLD\#0151B.PLA)
		93
		94	I289 Simple GAL architecture selected.
		95
		96
		97
		98
		99
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		101
		102	57 A1 A2 A3 A4' A5 A6' A7' IO1'
		103
		104
		105
		106	49 A1 A2 A3 A4 A5 A6' A7' IO1'
		107	50 A3' A4 A5 A6' A7' IO1'
		108
		109
		110
		111	FDC 32 A3 A4 A5' A6 A7' IO1' WA0 WA1
		112	33 A5' A6 A7 IO1' WA0' WA1'
		113
		114
		115
		116	17 A2' A3 A4' A5' A6 A7' IO1'
		117
		118	VDC 24 A1 A2 A3 A4' A5' A6 A7' IO1'
		119
		120	PIA 8 A2' A3 A4' A5 A6' A7' IO1'
		121
		122
		123	1 A2' A3 A4' A5' A6 A7' IO1' WT'
		124
		125
		126
		127	SIGNAL ASSIGNMENT
		128	Rows
		129
		130
		131
		132
		133	2. A1 0 - - - High
		134	3. A2 4 - - - High
		135	4. A3 8 - - - High
		136	5. A4 12 - - - High
		137
		138	7. A6 20 - - - High
		139	8. A7 24 - - - High
		140	9. IO1 28 - - - High
		141	10. - 32 - - -
		142	11. WA0 36 - - - High
		143	13. WA1 38 - - - High (Enable)
		144	14. WV 34 - - - High
		145	15. ATA0 31 56 8 3 Low
		146	16. ATA1 27 48 8 3 Low
		147	17. DMA 23 40 8 1 Low
		148	18. FDC - 32 8 3 Low
		149	19. VDC - 24 8 1 Low
		150	20. IOX 19 16 8 2 Low
		151	21. PIA 15 8 8 1 Low
		152	22. WAIT 11 0 8 2 Low
		153	23. WT 6 - - - High
		154	---- ----
		155	64 16 (25%)
		156
		157
		158	I200 No fatal errors found in source code (device phase).
		159	I201 No warnings.
		160
		161
		162
		163
		164	*
		165	QP24* QF2706* QV1024*
		166
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		169	L0320 11 11 10 11 01 11 10 11 01 11 10 11 10 11 10 11 11 11 11 11 *
		170	L0640 10 11 01 11 01 11 10 11 10 11 01 11 10 11 10 11 11 11 11 11 *
		171	L0680 11 11 10 11 01 11 10 11 10 11 01 11 10 11 10 11 11 11 11 11 *
		172	L0960 01 11 01 11 01 11 10 11 10 11 01 11 10 11 10 11 11 11 11 11 *
		173	L1280 11 11 11 11 01 11 01 11 10 11 01 11 10 11 10 11 11 11 01 01 *
		174	L1320 11 11 11 11 11 11 11 11 10 11 01 11 01 11 10 11 11 11 10 10 *
		175	L1360 11 11 11 11 11 11 11 11 11 11 10 11 01 11 10 11 11 11 10 10 *
		176	L1600 11 11 11 11 11 11 10 11 01 11 01 11 10 11 10 11 11 11 01 01 *
		177	L1920 10 10 01 11 01 11 01 11 01 11 10 11 10 11 10 11 11 11 11 11 *
		178	L1960 01 11 01 11 01 11 01 11 01 11 10 11 10 11 10 11 11 11 11 11 *
		179	L2000 11 11 11 11 10 11 01 11 01 11 10 11 10 11 10 11 11 11 11 11 *
		180	L2240 10 10 01 11 01 11 10 11 01 11 10 11 10 11 10 11 11 11 11 11 *
		181	L2280 01 11 01 11 01 11 10 11 01 11 10 11 10 11 10 11 11 11 11 11 *
		182	L2320 11 11 11 11 10 11 10 11 01 11 10 11 10 11 10 11 11 11 11 11 *
		183	L2560 00 00 00 00 00 11 00 00 00 11 00 01 00 11 01 01 00 11 00 01 *
		184	L2600 01 00 00 10 00 10 00 00 00 10 00 00 00 10 00 00 00 00 00 00 *
		185	L2640 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
		186	L2680 11 11 11 11 11 11 11 11 11 11 11 11 10 *
		187	C5132*
		188
		189	I202 7/22/17 5:40 pm (Saturday)
		190	I203 Memory usage 8K
		191	I204 Elapsed time 1 second
		192

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