| VIA 0 R65C22 (U11 in mainboard) - IRQ line 2 |
65C815 map |
$00FD00-$00FD0F |
| 65C02 map |
$FE00-$FE0F |
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| PA0 |
OUT |
Artificial address line DMA16 when DMA is active |
DMA can address only 64Kb. During DMA cycles this line select the low/high 64Kb of 128Kb buffer |
| PA1 |
OUT |
A low level enable the DMA |
After programming DMA, a "0" in this line enable the DMA. CPU cannot access buffer RAM and DMA&FDC registers. |
| PA2 |
OUT |
A low level (pulse) reset DMA |
If DMA chip is frozen, this line can reset it (hardware reset) |
| PA3 |
OUT |
A low level (pulse) reset FDC |
If FDC chip is frozen, this line can reset it (hardware reset) |
| PA4 |
OUT |
A low level (pulse) terminate DMA |
This line cause a software "Terminal Count" in DMA |
| PA5 |
OUT |
A low level (pulse) set a flip-flop (U16A/B) |
This flip-flop can be used to distinguish a hard reset from a soft reset |
| PA6 |
OUT |
A high level enable RS485 resistive termination |
This line enable the 120ohm termination in RS485-line (serial board) |
| PA7 |
OUT |
A low level reset the machine |
This line cause a hardware reset of the machine |
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| PB0 |
OUT |
A low level enable a wait state in the DMA chip |
With PHI2 = 4MHz the DMA work fine without wait states |
| PB1 |
OUT |
A low level enable a wait state in the FDC chip |
With PHI2 = 4MHz the FDC work fine without wait states |
| PB2 |
OUT |
A low level enable a wait state in the ACIA chip |
With PHI2 = 4MHz is mandatory to insert a wait state for ACIA access |
| PB3 |
OUT |
A low level enable a wait state in the ATA0 port |
With PHI2 = 4MHz the ATA work fine without wait states |
| PB4 |
OUT |
A low level enable a wait state in the ATA1 port |
With PHI2 = 4MHz the ATA work fine without wait states |
| PB5 |
OUT |
A low level enable a wait state in the VDC chip |
With PHI2 = 4MHz the VDC work fine without wait states |
| PB6 |
IN |
Square wawe at 1KHz |
This can be used as "clock" for Timer 2 (long time timeout) |
| PB7 |
OUT |
A low level enable a wait state in the CTC chip |
With PHI2 = 4MHz the CTC work fine without wait states |
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| CA1 |
IN |
Negative edge |
Can signal a timeout in channel 2 of CTC |
| CA2 |
IN |
Negative edge |
This pin is driven by keyboard controller (INT line) |
| CB1 |
IN |
Positive edge |
INT generated by FDC chip (no ISR need) |
| CB2 |
IN |
Negative edge |
Can signal a timeout in channel 1 of CTC |
| TIMER 1 |
Used for periodic IRQ |
Periodic interrupt every 20ms |
| TIMER 2 |
Used for timeout |
Timer 2 one-shot on PHI2 or 1KHz signal for long timeout (until 65 sec) |
| VIA 1 R65C22 (U12 in mainboard) - NMI line |
65C815 map |
$00FD10-$00FD1F |
| 65C02 map |
$FE10-$FE1F |
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| PA0 |
OUT |
A low level enable the VDC |
This line enable the RGB output from the VDC |
| PA1 |
OUT |
Select VDC dot clock |
Low = 16MHz, High = 20Mhz |
| PA2 |
OUT |
Select HSync polarity from VDC |
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| PA3 |
OUT |
Select VSync polarity from VDC |
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| PA4 |
OUT |
A low level (pulse) reset the keyboard |
This line cause a hardware rest of the keyboard |
| PA5 |
OUT |
Select polarity of ACIA line /CTS1 |
See serial board |
| PA6 |
OUT |
Select polarity of ACIA line /CTS2 |
See serial board |
| PA7 |
OUT |
A low level select RS485 |
See serial board. A low level switch channel 2 ACIA to RS485 interface |
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| PB0 |
OUT |
Select write cycle for register file |
If low the write in 74LS670 is qualified with PHI0, else with PHI2 |
| PB1 |
OUT |
Select DMA clock |
If low DMA clock = 4MHz, else DMA clock = 5MHz |
| PB2 |
OUT |
Select /CS or CS in VDC |
If low access to VDC is made by /CS, otherwise by CS |
| PB3 |
OUT |
Select write cycle for VDC |
If low the write in VDC is qualified with PHI0, otherwise with PHI2 |
| PB4 |
IN |
Negative pulse from ON/OFF push-button |
Power supply control |
| PB5 |
OUT |
Select write cycle for memory |
If low the write in memory is qualified with PHI0, otherwise with PHI2 |
| PB6 |
IN |
Square wawe at 1KHz |
This can be used as "clock" for Timer 2 (long time timeout) |
| PB7 |
OUT |
Square wawe at 1KHz |
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| CA1 |
IN |
Positive edge |
This line is driven by INT line of ATA 0 |
| CA2 |
IN |
Negative edge |
This pin is driven by keyboard controller (NMI line) |
| CB1 |
IN |
Positive edge |
This line is driven by INT line of ATA 1 |
| CB2 |
IN |
Negative edge |
This line is driven by the ON/OFF push-button. Can be used to swith-off computer by software |
| TIMER 1 |
Square wawe 1KHz on PB7 |
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| TIMER 2 |
Used for timeout |
Timer 2 one-shot on PHI2 or 1KHz signal for long timeout (until 65 sec) |